• Lecturer, Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi (August 2000 - December 2005)
• Assistant Professor, Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi (01/01/2006 – 26/08/2006)
• Assistant Professor (Senior Lecturer), Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi (27/08/2006 – 26/08/2009) 
• Assistant Professor (Reader), Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi (27/08/2009 - Till Date) 
• Associate Professor, Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi (27/08/2012 - 17/07/2018) 
• Professor, Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi (18/07/2018 - Till Date) 

• Convener-Research Centre 
• Convener – Science Foundation
• Convener  – College Research Committee
• Convener – Website Committee
• Convener – India Today NIELSEN Survey Committee for Science, Commerce and Arts
• Election Officer – DDU College Alumni Election for Executive 2016-2017.
• Member – UGC XIITH Plan Grants Committee 
• Member - Committee for ERP solution for paperless administrative, financial and academic management of the College

• Epitaxial Channel and Drain Engineered MOSFET
• Dual/ Tripple Material Gate (DMG/ TMG) MOSFET
• Silicon on Nothing (SON) MOSFET
• Insulated Shallow Extension (ISE) MOSFET
• Recessed Channel/ Grooved/ Concave Gate MOSFET 
• Tunnel FET
• Optically Controlled FET (OPFET)
• Mercuric Iodide (HgI2) X-Ray Detectors
• High Electron Mobility Transistor (HEMT)

Post Graduate Level (As Visiting Faculty)

Joint Supervision

Supervision of M. Phil dissertation

At College Level

Under Graduate Students (As Guide):   09

As IEEE Distinguished Lecturer delivered 30+ talks on the fllowing topics - 

• Dielectric Pocket MOSFET: A Novel Device Architecture;
• Embedded Insulator based Novel Nanoscaled Novel MOSFET Structures
• Tunnel Field Effect Transistor and its Application as Highly Sensitive and Fast Biosensor 
• Modeling and Simulation of Tunnel Field Effect Transistor Dual Material Junctionless Double Gate Transistor for Analog and Digital Performance
• Optimization of Asymmetric (Pi)π-Gate HEMT for Improved Reliability & Frequency Applications

Other publications (Edited works, Book reviews, Festschrift volumes, etc.)

1. Member - Editorial Board - Proceedings of 16th Asia Pacific Microwave Conference 2004, Department of Electronic Science, University of Delhi, Allied Publishers Pvt. Ltd. 2004, ISBN 81-7764-722-9.
2. Proceeding Editor - National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2006) from 22^nd March – 25^th March 2006, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India, ISBN: 81-8424-026-0
3. E-Proceeding Editor - National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2008) from 26^th September – 28^th September 2008, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India
4. Editor – Proceeding of the International Symposium on Microwave and Optical Technology (ISMOT)-2009, December 16-19, 2009.
5. Proceeding Editor - Third National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2010) held during January 30-31, 2010, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India, sponsored By University Grants Commission (UGC), Govt. of India

Book

• “Information Technology”, D. V. Singh, Shailender Kumar, Neeraj Tyagi, Pankaj Tyagi, Sanjeev Singh, Manoj Saxena and Ranjan Kumar, Universities Press, ISBN 9788173719004 (2013)

Book Chapter

• MOSFET Modeling, R. S. Gupta, Mridula Gupta and Manoj Saxena, Encyclopedia of RF and Microwave Engineering, John-Wiley & Sons, Inc. New Jersey, USA, March 2005, pp. 3278-3317, ISBN: 0-471-27053-9.

Abstracts in International Conferences

1. HEMGAS: A Novel Gate Workfunction Engineered Stacked Gate Oxide Concept for Sub-50 nm DG-MOSFET, Manoj Saxena, Subhasis Haldar, Mridula Gupta, and R. S. Gupta, 2nd International conference on Computer and Devices for communications, CODEC-2004, January 1-3, 2004 in Calcutta, India, pp. 155
2. Dual-Material Gate Asymmetric Oxide (DMGASYMOX) Stack MOSFET: A Novel Device Architecture for Improved Carrier Transport Efficiency and Reduced Hot Electron Effects, Kirti Goel, Manoj Saxena, Mridula Gupta, R. S. Gupta International Union of Radio Science (URSI), New Delhi, India, October 23-29, 2005.
3. Dual Material Gate (DMG) SOI-MOSFET with Dielectric Pockets: Innovative Sub-50 nm design for improved switching performance, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007) December 19 –21, 2007, Department of Physics & Astrophysics, University of Delhi, Delhi, pp. 109
4. Two-Dimensional Analytical Modeling and Simulation of Rectangular Gate Recessed Channel (RG-RC) Nanoscale MOSFET in Sub-50nm Regime, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007) December 19 –21, 2007, Department of Physics & Astrophysics, University of Delhi, Delhi, pp. 110.
5. TCAD investigation of a Novel MOSFET architecure of DMG ISE SON MOSFETs for ULSI era, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 18-19
6. Analytical analysis of subthreshold performance of sub-100 nm advanced MOSFET structures – An iterative approach, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 20-21
7. Modeling and 2-D simulation of Nanoscale SON MOSFET, Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 22-24
8. Performance advantage of air as buried dielectric in sub-100 nm silicon-on-nothing (SON) MOSFET with gate stack architecture, Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 25-26
9. Sub-threshold drain current performance assessment of MLGEWE-RC MOSFET for CMOS technology, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 27-28
10. RF performance assessment of L-DUMGAC MOSFET for furure CMOS technology in gigahertz regime, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 29-30
11. A Unified Two Dimensional Analytical Model of  optically Controlled Silicon On  Insulator  MESFET ( OPSOI ) for advanced channel materials, Rajni Gautam, Manoj Saxena, R.S. Gupta and Mridula Gupta, The International Conference on Fiber Optics and Photonics – PHOTONICS, December 11-15,2010, IIT Guwahati 
12. A 2-D Subthreshold Analytical model for Short Channel Effects in Nanowire MOSFETs (Si, Ge), Gaurav Mahajan, Rakhi Narang, Manoj Saxena, V.K. Chaubey, Nirma University International Conference on Engineering (NUiCONE) 2010, December 09-11, 2010, Nirma University, Ahmedabad
13. Fabrication and Time degradation study of mercuric iodide (Red) single crystal X-Ray detector, Kulvinder Singh and Manoj Saxena, International Symposium on Semiconductor Materials and Devices (ISSMD), M. S. University Vadodara, Gujarat, January 28-30, 2011 
14. Immunity Against Temperature Variability and Bias Point Invariability in Double Gate Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Materials for Advance Technologies, (ICMAT 2011), June 26, 2011 – July 01, 2011, Singapore(ABSTRACT appeared in Proceedings)
15. SiGe Metal Semiconductor Field Effect Transistor (MESFET) Photodectetor Having Tailorable Photoresponse Using Bandgap Engineering, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Materials for Advance Technologies, (ICMAT 2011), June 26, 2011 – July 01, 2011, Singapore (ABSTRACT appeared in Proceedings)
16. Simulation Study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for High Temperature Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Materials for Advance Technologies, (ICMAT 2011), June 26, 2011 – July 01, 2011, Singapore(ABSTRACT appeared in Proceedings)
17. Nanoscale Double Gate Silicon On Nothing (DGSON) MOSFET: Promising Device Design for Wide Range of Operating Temperatures, Vandana Kumari, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Conference on Latest Trends in Nanoscience and Nanotechnology (ICNSNT), 28th -29th  March 2011, Karnataka, India
18. Impact of a low bandgap material on the Linearity of a DG-TFET: A Comparative Study, Rakhi Narang, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Conference on Latest Trends in Nanoscience and Nanotechnology (ICNSNT), 28th -29th  March 2011, Karnataka, India
19. Study of Performance Degradation of the Nanoscale Cylindrical Surrounding Gate MOSFET due to Hot Carrier Induced Localized Charges, Rajni Gautam, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Conference on Latest Trends in Nanoscience and Nanotechnology (ICNSNT), 28th -29th  March 2011, Karnataka, India
20. High Sensitivity Photodetector Using Si/Ge/GaAs Metal Semiconductor Field Effect Transistor (MESFET), Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, OPTICS 2011, May 23-25, 2011, Calicut, Kerala, India 
21. Effect of Temperature and Gate Stack on the Linearity and Analog Performance of Double Gate Tunnel FET, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, The Second International Workshop on VLSI (VLSI 2011) in conjunction with (NECOM-2011), Venue: The Park Hotels, July 15 ~ 17, 2011, Chennai, India. 
22. Channel Material Engineered Nanoscale Cylindrical Surrounding Gate MOSFET With Interface Fixed Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, The Second International Workshop on VLSI (VLSI 2011) in conjunction with (NECOM-2011), Venue: The Park Hotels, July 15 ~ 17, 2011, Chennai, India.
23. Drain Current Model of Nanoscale Dual Material Gate (DMG) MOSFET including interfacial hot-carrier-induced degradation effect", Mini, Vandana Kumai, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Microwaves, Antenna, Propagation and Remote Sensing, ICMARS-2011, Jaipur, India
24. Influence of Localised charges on the temperature sensitivity of Si nanowire MOSFET, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, XVI International Workshop on the Physics of Semiconductor Devices, IWPSD 2011, December 19-22, 2011, IIT Kanpur
25. Temperature Dependent RF/microwave Characteristics of Nanowire Surrounding Gate MOSFET with Localised Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta,  International Conference on Nanoscience and Technology (ICONSAT – 2012), January 20 to 23, 2012 at Hyderabad, India.
26. Dynamic Performance Comparison of p-i-n and p-n-p-n Tunnel Field Effect Transistor and Impact of Gate Drain underlap , Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta,  International Conference on Nanoscience and Technology (ICONSAT – 2012), January 20 to 23, 2012 at Hyderabad, India.
27. Nano-scale Empty Space in Double Gate (ESDG) MOSFET for High Performance Digital Applications: A Theoretical Study, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta,  International Conference on Nanoscience and Technology (ICONSAT – 2012), January 20 to 23, 2012 at Hyderabad, India. 
28. Impact of temperature variations on the device and circuit performance of Tunnel FET - A Simulation Study, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, NANOCON 2012 – Second International Conference on Nanotechnology - Innovative Materials, Processes, Products and Applications  during October 18-19 2012, at Bharati Vidyapeeth University, Pune, India, pp.99 
29. Comparative Study of Silicon On Nothing and III-V On Nothing Architecture for High Speed and Low Power Analog and RF/Digital Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, NANOCON 2012 – Second International Conference on Nanotechnology - Innovative Materials, Processes, Products and Applications  during October 18-19 2012, at Bharati Vidyapeeth University, Pune, India, pp.105 
30. Gate All Around MOSFET with Catalytic Metal Gate for Gas Sensinga Applications, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, NANOCON 2012 – Second International Conference on Nanotechnology - Innovative Materials, Processes, Products and Applications  during October 18-19 2012, at Bharati Vidyapeeth University, Pune, India, pp.106 
31. Drain Current Model for Hetero-Dielectric based TFET Architectures: Accumulation to Inversion Mode Analysis , Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, NANOCON 2014 – Third International Conference on Nanotechnology during October 14-15, 2014 organized by Bharati Vidyapeeth University, Pune, India at  Le-Meridien Hotel, Pune  
32. Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET, Vandana Kumari, Manoj Saxena, Mridula Gupta, NANOCON 2014 – Third International Conference on Nanotechnology during October 14-15, 2014 organized by Bharati Vidyapeeth University, Pune, India at  Le-Meridien Hotel, Pune 
33. pH sensing Characteristics of Silicon on Insulator (SOI) Junctionless (JL) ISFET, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, NANOCON 2014 – Third International Conference on Nanotechnology during October 14-15, 2014 organized by Bharati Vidyapeeth University, Pune, India at  Le-Meridien Hotel, Pune 
34. TCAD Assessment of Nanoscale Double Gate RingFET (DG-RingFET) Architecture: Analog and Linearity Performance Investigation for RFIC Design , Sachin Kumar, Vandana Kumari, Manoj Saxena, Mridula Gupta, NANOCON 2014 – Third International Conference on Nanotechnology during October 14-15, 2014 organized by Bharati Vidyapeeth University, Pune, India at  Le-Meridien Hotel, Pune 
35. Numerical Analysis of Variability effects in Nanogap Embedded Dielectric Modulated Field Effect Transistor, Rakhi Narang, Manoj Saxena and Mridula Gupta, NANOCON 2014 – Third International Conference on Nanotechnology during October 14-15, 2014 organized by Bharati Vidyapeeth University, Pune, India at  Le-Meridien Hotel, Pune
36. Linearity and analog performance realization of energy efficient TFET based architectures: An Optimization for RFIC Design, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, International Conference on Emerging Electronics (ICEE) held at J N Tata Auditorium, Indian Institute of Science during December 4-6, 2014
37. Modeling and Simulation of  Nanoscale III-V based Tri Gate Stack MOSFET on Nothing for Improved Analog and Digital Applications, Vandana Kumari, Manoj Saxena, Mridula Gupta, International Conference on Recent Advances in Nanoscience and Nanotechnology (ICRANN-2014), Jawahar Lal Nehru University, New Delhi held during December 15-16, 2014
38. Dielectric Pocket Tunnel FET: A Reliable Alternative, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, International Conference on Recent Advances in Nanoscience and Nanotechnology (ICRANN-2014), Jawahar Lal Nehru University, New Delhi held during December 15-16, 2014
39. Analysis of Cylindrical Gate Junctionless Tunnel Field Effect Transistor (CG-JL-TFET), Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta,  12th IEEE India International Conference, INDICON 2015, on Electronics, Energy, Environment, Communication, Computer, Control, (E3-C3) held during December 17-20, 2015 at Jamia Millia Islamia, New Delhi, India (Received Best Paper Award) (Presented)
40. Merits of designing  Tunnel Field Effect Transistors with Underlap near Drain region, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, 12th IEEE India International Conference, INDICON 2015, on Electronics, Energy, Environment, Communication, Computer, Control, (E3-C3) Held during December 17-20, 2015 at Jamia Millia Islamia, New Delhi, India (Presented)
41. Investigation of III-V Compound Semiconductor Materials on Analog performance of Nanoscale RingFET, Sachin Kumar, Vandana Kumari, Manoj Saxena, Mridula Gupta, 12th IEEE India International Conference, INDICON 2015, on Electronics, Energy, Environment, Communication, Computer, Control, (E3-C3) held during December 17-20, 2015 at Jamia Millia Islamia, New Delhi, India
42. Study of Gate Underlap Dielectric Modulated Double Gate Junctionless MOSFET as a Biosensor, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, 18th International Workshop on Physics of Semiconductor Devices (IWPSD 2015) held during December 7-10, 2015 at INDIAN INSTITUTE OF SCIENCE,  Bangalore, India.
43. Physical Insights into Double Gate (DG) p-i-n TFET Operating States: Modeling and Simulation Study, Upasana, Sakshi Gupta, Rakhi Narang, Manoj Saxena and Mridula Gupta, 18th International Workshop on Physics of Semiconductor Devices (IWPSD 2015) held during December 7-10, 2015 at INDIAN INSTITUTE OF SCIENCE,  Bangalore, India.
44. Analysis of Gate Underlap Channel Junctionless Double Gate MOSFET as a Sensor, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, 6th International Conference on Computers and Devices for Communication (CODEC-15) held at Swissotel Kolkata, India during December 16-18,2015.
45. Modeling and Simulation Study of Short Gate  TFET Architecture Considering the Impact of Mobile Charge Carriers, Understanding Device Physics in Different Operational Regimes, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, 6th International Conference on Computers and Devices for Communication (CODEC-15) held at Swissotel Kolkata, India during December 16-18,2015.
46. Modeling the Impact of Gate Misalignment in Tunnel Field Effect Transistors" authored by Upasana, Sakshi Gupta, Rakhi Narang, Manoj Saxena and Mridula Gupta, International Conference on Microelectronics Devices, Circuits and Systems (ICMDCS 2017) held at the VIT University, Vellore India from 10th to 12th August 2017
47. Analytical Modeling and Simulation study of Homo and Hetero III-V Semiconductor based Tunnel Field Effect Transistor, M. Lakshmi Varshika, Rakhi Narang, and Manoj Saxena, accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
48. Study of Extended Back Gate Double Gate JunctionLess Transistor: Theoretical and Numerical Investigation, Vandana Kumari, Abhineet Sharan Manoj Saxena, Mridula Gupta, accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
49. Analytical Model for Tapered Gate Electrode Double Gate MOSFET Incorporating Fringing Field Effects, Rakhi Narang, Gokulnath R, Mridula Gupta, and Manoj Saxena, accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
50. Investigation of sensitivity of Gate Underlap Junctionless DG MOSFET for Biomolecules, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
51. Floating Gate Junction-less Double Gate Radiation Sensitive Field Effect Transistor (RADFET) Dosimeter: A Simulation Study, Avashesh Dubey, Rakhi Narang, Manoj Saxena, and Mridula Gupta, accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
52. Optically Controlled Silicon On Nothing MOSFET-Numerical Simulation, Vandana Kumari, Manoj Saxena, Mridula Gupta accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
53. Simulation Study on Stability aspect of Dual Metal Dual Dielectric based TFET Architectures against Temperature Variations, Upasana, Rakhi Narang, Manoj Saxena, Mridula Gupta accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.

Paper Published in National conferences: -

1. Two-Dimensional Analytical Modeling and Simulation of DMG-EPI MOSFET, Kirti Goel, Manoj Saxena, Mridula Gupta and R. S. Gupta, National conference on VLSI Design & Technology, April 12-13, 2004, Bharati Vidyapeeth’s College of Engineering, Paschim Vihar, New Delhi, India.
2. Two-Dimensional Analytical Modeling and Simulation of a novel structure Triple-Material Gate Stack (TRIMGAS) MOSFET, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, ELECTRO-2005, Emerging Trends in Electronics, BHU, Varanasi, February 3-5, p.134-137, 2005.
3. Two-Dimensional Analytical Modeling and Simulation of Multiple Material Gate Oxide Stacked MOSFET, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, National Conference on Integrated Broad Band Digital Systems and Networks, NIEC, Delhi, March 18-19, 2005
4. RF Performance Investigation of Gate Stacked Insulated Shallow Extension (ISE) MOSFET and Bulk: A Comparative Study, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Proceeding of Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 254-258
5. Design and FPGA realization of Direct Sequence-Spread Spectrum (DS-SS) BPSK Modulator using a Five Stage Gold Code Generator, Rishu Chaujar, Ravneet Kaur, Manoj Saxena and R. S. Gupta, Proceeding of Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 213-216.
6. Scrambled Sequence FPGA based Direct Sequence Spread Spectrum BPSK Modulator: 10 Stage Analysis, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, National Conference on Recent Trends in Electronics and Information Technology, (RTEIT 2006), pp 334-337, 28-29 July 2006, Maharashtra, India.
7. Exploring the Effect of Negative Junction Depth on Electrical Behaviour of Sub-50-Nanometer Concave DMG MOSFET: A Simulation Study, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), pp. 123-125, 6-8 October 2006, Jaipur, India.
8. Lateral Channel Engineered Structure- Insulated Shallow Extension (ISE) MOSFET: DC and RF Performance Investigation, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), pp. 119-122, 6-8 October 2006, Jaipur, India.
9. Effect of transport property on the performance of insulated shallow extension gate stack (ISEGaS) MOSFET, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, pp. 52-57, August 17-18, 2007, Punjab Engineering College, Chandigarh, India
10. New Concave MOSFET with Transverse Dual Material Gate (T-DMG) in Sub-50nm Regime: A Simulation Study, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, pp. 33-37, August 17-18, 2007, Punjab Engineering College, Chandigarh, India (Best Student Paper Award)
11. A 2-D Analytical Model for Gate Misalignment Effects on Graded Channel DG FD SOI n-MOSFET, Rupendra Kumar Sharma, Manoj Saxena, Mridula Gupta and R. S. Gupta, Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, August 17-18, 2007, Punjab Engineering College, Chandigarh, India
12. Development Board-Level Experimentation and Simulation of FPGA based DEBPSK DSSS Modulator: Implementation of 10-Chip Gold Code Sequence Generator, Rishu Chaujar, Ravneet Kaur, Manoj Saxena and R. S. Gupta, Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008) September 26-28, 2008 in New Delhi, India, pp. 255-261.
13. Simulation of a Novel ISE MOSFET with Gate Stack Configuration, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008) September 26-28, 2008 in New Delhi, India, pp. 291-296.
14. Solution to CMOS technology for high performance analog applications: GEWE-RC MOSFET , Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R. S. Gupta, 2^nd  National Workshop on Advanced Optoelectronic Materials and Devices, AOMD 2008, art. no. 5075707, pp. 201-205.
15. Effect of temperature variation on various parameters in Insulated Shallow Extension Silicon On Nothing(ISE-SON)MOSFET:A simulation study, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, National Conference and Workshop on Recent Advances in Modern Communication Systems and Nanotechnology (NCMCN – 2011), January, 06-08, 2011
16. Performance Comparison of Silicon and SiGe based Double Gate Tunneling Field Effect Transistor with gate stack architecture, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, National Conference and Workshop on Recent Advances in Modern Communication Systems and Nanotechnology (NCMCN – 2011), January, 06-08, 2011
17. Impact of Localised Charges on the performance of the Si Nanowire Surrounding Gate MOSFET, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, National Conference and Workshop on Recent Advances in Modern Communication Systems and Nanotechnology (NCMCN – 2011), January, 06-08, 2011
18. Investigation of Linearity Performance of a Double Gate Band to Band Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, 15^th VLSI Design and Test Symposium, July 7-9, 2011, Wipro Technologies, Pune, India
19. Analog Performance of Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET: Simulation study, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, 15^th VLSI Design and Test Symposium, July 7-9, 2011, Wipro Technologies, Pune, India
20. A Wide Temperature Range ( 50-500K ) Analysis For Nanoscale Surrounding Cylindrical Gate MOSFET With Localised Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, 15^th VLSI Design and Test Symposium, July 7-9, 2011, Wipro Technologies, Pune, India
21. Modeling and Simulation of Dielectric Pocket Silicon On Nothing (DiPSON) MOSFET, Neha Bhushan and Manoj Saxena, 99^th  Indian Science Congress held at KIIT University, Bhubneswar during Jan 03 – 07, 2012
22. Impact of Insulating Layers on Single and Double Gate MOSFET for Improved Short Channel Effect and Hot Carrier Reliability , Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, First National Conference on Recent Developments in Electronics (NCRDE 2013), Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013
23. High Performance Low Power 6T RAM Cell Using Gate-All Around (GAA) MOSFET , Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, First National Conference on Recent Developments in Electronics (NCRDE 2013), Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013
24. Performance Investigation of Silicon Nanowire Tunnel FET for Analog and Digital Applications, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, First National Conference on Recent Developments in Electronics (NCRDE 2013), Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013
25. NI MULTISIM Implementation of Memristor Based Secured Communication System, Khushwant Sehra Poonam Kasturi Mamta Amol Wagh and Manoj Saxena, Proceedings of National Conference on Advancements in Electronics and Computer Applications NCAECA 2016 (UGC and DiETY Sponsored) held during Feb 04-05, 2016 at Shaheed Rajguru College of Applied Sciences, University of Delhi. Pp. 19-24, ISBN 978-93-5254-496-7 published by M/s Paramount Publishing House
26. Study of Gate and Drain Controllability over Double Gate (DG)Tunnel FETs through Modeling and Simulation, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, Conference Proceedings of Second National Conference on Recent Developments in Electronics (NCRDE-2017), pp. 160-165, ISBN: 978-81- 933475-3- 9
27. Impact of High-K Gate Dielectric on Double Gate RingFET (HK-DG-RingFET) Architecture, Sachin, Vandana Kumari, , Manoj Saxena and Mridula Gupta, Conference Proceedings of Second National Conference on Recent Developments in Electronics (NCRDE-2017), pp. 177-180, ISBN: 978-81- 933475-3- 9
28. Two-Dimensional Surface Potential Model for Gate All Around Junctionless Tunnel Field-Effect Transistor, Ajay, rakhi Narang, Manoj Saxena and Mridula Gupta, Conference Proceedings of Second National Conference on Recent Developments in Electronics (NCRDE-2017), pp. 154-159, ISBN: 978-81- 933475-3- 9
     

Abstracts in National Conferences

1. Generation Of Arbitrary Waves Using Arduino Due, Arun Chahar, Poonam Kasturi and Manoj Saxena , Poster Presentation in THINK NANO 2016 – National Student Symposium organized by Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science, Bangalore held during March 31, 2016 - April 01, 2016 at IISc, Bangalore
2. Integration of Mem-Element with SCR based Rectifiers, Khushwant Sehra, Gaurav Kumar Shakya, Poonam Kasturi and Manoj Saxena, Poster Presentation in THINK NANO 2016 – National Student Symposium organized by Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science, Bangalore held during March 31, 2016 – April 01, 2016 at IISc, Bangalore
3. Simulation and Experimental Verification of Memristor Based XOR Gate, Arushi Gupta, Rishav Kumar Pandey, Divya Goel, Poonam Kasturi, Mamta Amol Wagh, Manoj Saxena, Poster Presentation in THINK NANO 2016 – National Student Symposium organized by Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science, Bangalore held during March 31, 2016 – April 01, 2016 at IISc, Bangalore
4. Smart Traffic System Design Based On PIC Microcontroller, Himanshu Bhardwaj, Samaa Manzoor Wani, Poonam Kasturi  and Manoj Saxena, Poster Presentation in THINK NANO 2016 – National Student Symposium organized by Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science, Bangalore held during March 31, 2016 – April 01, 2016 at IISc, Bangalore

• Joint Secretary and Member - Technical Review Committee - 16th Asia-Pacific Microwave Conference (APMC’2004), University of Delhi, December 15 - 18, 2004, New Delhi, India
• Member - Local organizing committee - India-Japan Workshop (IJW-2006) on ZnO Materials and Devices, December 18-20, 2006 sponsored by DST (New Delhi) - JSPS (Japan) organized by Department of Electronic Science, University of Delhi South Campus
• Secretary Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program
• Secretary The 18th WIMNACT(Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology)-New Delhi, India - Mini-Colloquia on Compact Modeling and Fabrication techniques of advance MOSFET/ HEMT structures, June 04-05, 2009 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program
• Symposium secretary International Symposium on Microwave and Optical Technology (ISMOT)-2009 , December 16-19,2009 in Hotel Ashok, New Delhi, India  
• Program Committee Member The Seventh International Conference on Distributed Computing and Internet Technology, Bhubaneswar, India, 9 – 12 February 2011
• Program Committee Member International Conference on Soft Computing for Problem Solving (SoCProS 2011), Roorkee, India, December 16-18, 2011 http://www.mirlabs.net/socpros11/ 
• Convener Science Academies Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates, February 17-18, 2012, SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, Dhaula Kuan, New Delhi
• Member-Organizing Committee International MOS-AK/GSA (India) workshop,  March 16-17, 2012 in JIIT University, Noida, Uttar Pradesh, India
• Member Technical Program Committee Seventh International Conference on “Bio-Inspired Computing: Theories and Application, 2012 (BIC-TA 2012)” to be held at ABV-Indian Institute of Information Technology and Management Gwalior during December 14 - 16, 2012. http://www.iiitm.ac.in/bicta2012/
• Secretary Mini-Colloquia on "Compact Modelling Techniques for Nanoscale Devices and Circuit Analysis” Organized by IEEE EDS-Delhi Chapter, New Delhi, India during March 14-15, 2012 held at SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, New Delhi, 110021. The Mini-Colloquia was sponsored by the IEEE Electron Devices Society under its Distinguished Lecturer Program
• Technical Program Committee Member 10th International Conference on Distributed Computing and Internet Technologies, 6th - 9th February, 2014, Bhubaneswar, Odisha, India.
• Secretary Mini Colloquia on “Compact Modelling Techniques for Nanoscale Devices and Circuit Analysis” on January 13, 2015, University of Delhi South Campus
• Member-Technical Program Committee International Conference on 14th -15th Jan, 2016 themed on “Cloud System and Big Data Engineering” at Amity University Uttar Pradesh Noida Campus, http://www.gtie2016.com/committees.html#2  ​
• International Steering Committee Member – 2019 IEEE International Conference on Modeling of System Circuits and Devices (MOS-AK India 2019) organized by joint chapter of CAS/ED Societies IEEE Hyderabad Section, IIT Hyderabad during February 25-27, 2019.
• Conference Secretary - XVII International Symposium on Microwave and Optical Technology, ISMOT 2020 to be held during December 15-18, 2020 in New Delhi India.

National Events

1. Member - Organizing Committee National Symposium on recent advances in microwaves and light waves (NSAML’03) University of Delhi South Campus, New Delhi, October 2003.
2. Treasurer and Member Organizing Committee Short course on Spice Models for Advanced VLSI Circuit Simulation organized by Department of Electronic Science, University of Delhi South Campus, Dec. 11-12, 2005
3. Secretary and Member-Technical Programme Committee National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2006) from 22nd March – 25th March 2006, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India
4. Co-convener and Secretary - National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2008) from 26th September – 28th September 2008, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India
5. Coordinator - Two-Days Workshop On Quantum Mechanics: Theory and Application during November 21-22, 2008, Organized by Forum for Interdisciplinary Application in Sciences (FiDAS) Deen Dayal Upadhyaya College, University of Delhi, New Delhi Sponsored by Delhi Chapter of the National Academy of Sciences, India.
6. Co-convener and Secretary - Three days Workshop on Futuristic trends of Quality Control in Information Security Management, Sponsored by CSIR, Govt. of India, October 09-11, 2009 organized by Forum for Interdisciplinary Application in Sciences (FiDAS) Deen Dayal Upadhyaya College, University of Delhi, New Delhi
7. Member-Organizing Committee National Seminar and Workshop on Integrating Multiple Technologies to Support Teaching and Learning, September 24-26, 2009 organized by Department of Electronics, Maharaja Agarasen College, University of Delhi and sponsored by UGC, Govt. of India
8. Coordinator - First One-Day National Workshop on Einstein & Special Theory of Relativity, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 06, 2009
9. Coordinator - Second One-Day National Workshop on Einstein & Special Theory of Relativity, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 07, 2009
10. Coordinator - Two-Day National Workshop on Fiber Optics and Applications, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 28-29, 2009
11. Co-convener and Secretary - Third National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2010) held during January 30-31, 2010, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India, sponsored By University Grants Commission (UGC), Govt. of India
12. Convener - First National Workshop On Recent Trends in Semiconductor Devices and Technology, Jointly Organized By Aryabhatta Science Forum, Deen Dayal Upadhyaya College, University of Delhi And IEEE EDS Delhi Chapter, New Delhi, Supported By Integrated Microsystem, Gurgaon, India, Society for Microelectronics and VLSI, New Delhi, February 12-13, 2010
13. Convener - Second National Workshop On Recent Trends in Semiconductor Devices and Technology, Jointly Organized By FiDAS, Deen Dayal Upadhyaya College, University of Delhi And IEEE EDS Delhi Chapter, New Delhi, Supported By DRDO, Govt of India and Integrated Microsystem, Gurgaon, India held during September 17-18, 2010
14. Convener - Second National Workshop On Quantum Mechanics: Theory and Application Organized By FiDAS, Deen Dayal Upadhyaya College, University of Delhi, Sponsored By CSIR, Govt of India Supported By IEEE EDS Delhi Chapter, New Delhi and The National Academy of Sciences, India, - Delhi Chapter held during Oct. 22-23, 2010 and October 29-30, 2010
15. Workshop Coordinator - Three Day Joint Science Academies Lecture Workshop On Frontier in Physics, January 21-23, 2011 jointly Organized by FIDAS, Deen Dayal Upadhyaya College and IEEE EDS Delhi Chapter at SP Jain centre, University of Delhi South Campus, New Delhi
16. Secretary - First National Workshop On Numerical Methods and Differential Equations in Computational Science (NUMDECS-2011), February 01-05, 2011 Organized by FIDAS, DDU College, Sponsored and Supported by University Grants Commission (UGC), Govt. of India
17. Member-Organizing Committee NATIONAL SEMINOR ON RECENT ADVANCES IN MICROELECTRONIC DEVICES Organized by Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, Sec-22, Rohini, Delhi-110086 sponsored by Defence Research and Development Organization Ministry of Defence, Government of India.
18. Convener Science Academies Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates, February 17-18, 2012, SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, Dhaula Kuan, New Delhi
19. Convener Science Academies Lecture Workshop On Joint Academies Lecture Workshop On History, Aspects and Prospects of Electronics in India, October 12-13, 2012,  SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, Dhaula Kuan, New Delhi
20. Convener Lecture Workshop on Trans-disciplinary Areas of Research and Teaching by  Shanti Swaroop Bhatnagar Awardee, February 01-02, 2013 organized by Deen Dayal Upadhyaya College, University of Delhi sponsored by Council of Scientific and Industrial Research (CSIR), New Delhi and supported by IEEE EDS Delhi Chapter
21. Convener Third National Workshop On Recent Trends in Semiconductor Devices and Technology, January 19-20, 2013 Jointly organized by Deen Dayal Upadhyaya College, University of Delhi and IEEE EDS Delhi Chapter, New Delhi Sponsored By Defence Research and Development Organization (DRDO), Ministry of Defence, Government of India. Venue: SP Jain Centre, University of Delhi South Campus, Benito Juarez Road, Dhaula Kuan, New Delhi
22. Secretary First National Conference on Recent Developments in Electronics (NCRDE 2013) is being organized by IEEE EDS Delhi Chapter. The conference will be held at Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013 
23. Convener Fourth National Workshop On Recent Trends in Semiconductor Devices and Technology, September 12-13, 2014 organized by Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi Sponsored By Defence Research and Development Organization (DRDO), Ministry of Defence, Government of India. 
24. Convener On October 17, 2014, One Day Seminar on “Women in Science: A career in Science”, Organized by Silizium-Electronics Society, Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, supported by IEEE EDS Delhi Chapter and Science Education Panel, Indian Acdemy of Sciences, Bangalore
25. Convener Second Lecture Workshop on Trans-disciplinary Areas of Research and Teaching by Shanti Swaroop Bhatnagar Awardee, January 30-31, 2015 organized by Deen Dayal Upadhyaya College, University of Delhi sponsored by Council of Scientific and Industrial Research (CSIR), New Delhi and supported by IEEE EDS Delhi Chapter
26. Convener - One Day Symposium to Celebrate International Year of Light held on October 28, 2015.
27. Convener - Third Workshop on Quantum Mechanics: Theory and Application during March 13-14, 2016 organized by Silizium-Electronics Society, Deen Dayal Upadhyaya College.
28. Activities organized as Convener-Science Foundation https://dducollegedu.ac.in/ViewpagePAnel.aspx?MenuId=Q8dDQco9jeHkDT6i1aMwZU9NcU8mu5CI
29. Activities organized as Program Coordinator-DBT Star College Program https://dducollegedu.ac.in/Viewtopics.aspx?MenuId=OGlqRo1PqJzQF5Yfpvx5Gbc____2OFSeIFK

Participation as Paper/Poster Presenter

• A 2-D Subthreshold Analytical model for Short Channel Effects in Nanowire MOSFETs (Si, Ge), Gaurav Mahajan, Rakhi Narang, Manoj Saxena, V.K. Chaubey, Nirma University International Conference on Engineering (NUiCONE) 2010, December 09-11, 2010, Nirma University, Ahmedabad

1. Program Coordinator – DBT Star College worth Rs. 1.04 Crores (2018 - )
2. Co-Principal Investigator in Contract for Acquisition of Research Services (CARS), DRDO sponsored project entitled “Layout Optimization and Thermal analysis swltchlng applicatlons and LNA Design” 2019-2020 worth Rs. 23 Lakhs (Feb 2019 - )
3. Co-Principal Investigator in CSIR, Govt. of India sponsored major research project entitled Modelling and Simulation Gate Electrode Engineered  and Dielectric Pocket Steep Threshold swing Device for Low Power Digital Circuit Design and Optical Applications(Letter No. 22(0724)/17/EMR-II dt May 16, 2017) worth Rs. 
4. Co-Principal Investigator in UGC, Govt. of India sponsored research project entitled Physics Based Modeling and Simulation of Channel Material Engineered Ring FET for Sensing Applications worth Rs. 17,23,000/- On Going - (August 01, 2015 - August 2018)
5. Principal Investigator in a University of Delhi Sponsored Project under Innovation Project Scheme  entitled “Mathematical Modeling and Simulation of Circular and Non-Circular Gate Geometry Junctionless Nanoscale Transistor and co-integration with Memristor Based Electronic Circuits” worth Rs. 4,00,000/- On Going - (October 01, 2015 – November 2016)
6. Principal Investigator in a University of Delhi Sposnored Project under Innovation Project Scheme entitled Analytical Modeling, Simulation and Verification of Emerging Nanoscale MULTIGATE Device Structures and Study of Government’s Initiatives for Growth of Electronics In India, Project Code – 202 (2013) worth Rs. 5,50,000/- Completed - (November 2013 – February 2015)
7. Co-Project Investigator in a DST Sponsored Project entitled Analytical Modelling and Simulation of Sub-100 nm Advance Tunnel FET architecture for RF/ Microwave and Biosensing Applications, (SR/S3/EECE/0062/2012) worth Rs. 31,14,000 Completed - (September 2012 – October 2014)
8. Co-Project Investigator in a DRDO sponsored Project entitled Analytical Modeling, Simulation and Characterization of Silicon Gate All Around Nanowire MOSFET for ULSI (Ultra Large Scale Integration) Circuit Applications worth Rs. 30,68,000 Completed - (April 2012 – March 2015)
9. Co-Project Investigator in a DRDO sponsored Project entitled Physics Based Modeling and Simulation of Sub-100 nm recessed channel (RC) and insulated shallow extension (ISE) MOSFET with gate electrode work function engineering structures for high performance applications (ERIP/ER/0803693/M/01/1258) worth Rs. 4.70 lakhs Completed - (October 2010 – July 2012)
10. Co-Principal Investigator in UGC, Govt. of India sponsored research project entitled Modeling and simulation of Nanoscale Dual Material Gate Insulated Shallow Extension Silicon on Nothing MOSFET for Low voltage low power applications (F. No. 36-258/2008(SR)) worth Rs. 9,22,800  Completed - (May 2009 – April 2012)
11. Co-Project Investigator in a DRDO sponsored Project entitled Physics Based Modeling Simulation and Electrical Characterization of a Novel Device Architecture: Silicon-On-Nothing MOSFET for Sub-100 nm Device Dimensions (No. ERIP/ER/0303417/M/01) worth Rs. 31.68 Lakhs Completed - (April-2004-December 2007) 

• Received Smt. Shanti Devi Bhargava Memorial Gold medal for being best candidate in the M. Sc Examination in Electronics in 2000
• Name appeared in the Golden List of IEEE Transactions on Electron Devices Reviewers for year 2005, 2006, 2008, 2009 and 2010.
• Received outstanding EDS Volunteer recognition from EDS Chapters in the region in 2012.
• Received Meritorious Teacher by the Govt. of NCT of Delhi for the Year 2014, based on evaluation comprising of Student Evaluation, Result Evaluation, Self Appraisal and Evaluation by the Principal.  
• Regional Editor South Asia – IEEE EDS News Letter (2015-2017, 2018-)
• Senior Member - IEEE
• IEEE EDS Distinguished Lecturer (2016 - )
• Fellow IETE (2017 - )
• Member-EDS Board of Governers, USA (2018-2020)

• Indian Academy of Sciences, Platinum Jubliee Meeting, Bangalore, November 12-14, 2009
• Bhabha Centenary Symposium, Tata Institute of Fundamental Research,  Mumbai, India, December 03-05, 2009
• Indian Academy of Sciences 76th Annual Meeting 2010, Goa, 12 to 14 November 2010

B. Sc. Hons. Electronics – CBCS Scheme University of Delhi 2015-2018 - Analog Electronics - Course Outline and Suggested Books