Photograph Name Dr MANOJ SAXENA
Email Id saxenamanoj77@gmail.com Date Of Join
Designation Associate Professor Mobile No --
Address
Web Page
Educational Qualifications
Degree Institution Year
Ph. D Electronics Department of Electronic Science, University of Delhi 2006
M. Sc Electronics Department of Electronic Science, University of Delhi 2000
B. Sc. Hons Electronics Rajdhani College, University of Delhi 1998
Career Profile
  • Lecturer, Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi (August 2000 - December 2005)
  • Assistant Professor, Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi (01/01/2006 – 26/08/2006)
  • Assistant Professor (Senior Lecturer), Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi (27/08/2006 – 26/08/2009) 
  • Assistant Professor (Reader), Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi (27/08/2009 - Till Date) 
  • Associate Professor, Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi (27/08/2012 - Till Date) 
Administrative Assignments
Year 2019 – 2020
  • IQAC Coordinator (December 08, 2017 - )
  • Coordiinator-MHRD-IIC-DDUC Chapter
  • Treasurer-Staff Association (Teaching) Till September 2019
  • Coordinator-DBT Star College Scheme
  • Nodal Officer Acadmic Activities - RUSA
  • Convener – Science Foundation
  • Member – College Research Committee (December 08, 2017 - December 2019 )
  • Member –NIRF Committee
  • Member-Time Table Committee
  • Member-Admission Committee
Year 2018 – 2019
  • IQAC Coordinator (December 08, 2017 - )
  • Coordiinator-MHRD-IIC-DDUC Chapter
  • Treasurer-Staff Association (Teaching)
  • Cordinator-DBT Star College Scheme
  • Nodal Officer Acadmic Activities - RUSA
  • Convener – Science Foundation
  • Convener – College Research Committee (Till December 08, 2017)
  • Member – College Research Committee (December 08, 2017 - )
  • Convener – Website Committee
  • Member –NIRF Committee
  • Member – UGC XIITH Plan Grants Committee
  • Member-Time Table Committee
Year 2017 – 2018
  • Convener-Research Centre
  • Nodal Officer Acadmic Activities - RUSA
  • Convener – Science Foundation
  • Convener  – College Research Committee
  • Convener – Website Committee
  • Convener – India Today NIELSEN Survey Committee for Science, Commerce and Arts
  • Election Officer – DDU College Alumni Election for Executive 2016-2017.
  • Member –NIRF Committee
  • Member – UGC XIITH Plan Grants Committee
  • Member - Committee for ERP solution for paperless administrative, financial and academic management of the College
  • Member-Time Table Committee
  • Member-Admission Committee for Electronics
Year 2016 – 2017
  • Convener-Research Centre 
  • Convener – Science Foundation
  • Convener  – College Research Committee
  • Convener – Website Committee
  • Convener – India Today NIELSEN Survey Committee for Science, Commerce and Arts
  • Election Officer – DDU College Alumni Election for Executive 2016-2017.
  • Member – UGC XIITH Plan Grants Committee 
  • Member - Committee for ERP solution for paperless administrative, financial and academic management of the College
 
Year 2015 – 2016
Teacher-in-Charge – Department of Electronics 
Convener-Research Centre 
Convener – Science Foundation
Convener  – College Research Committee (November 19, 2015 - )
Convener – Website Committee
Convener – Career Counseling and Placement Cell
Convener-Admission Committee for Electronics
Member- Academic Development Committee
Member - Library Committee
Member – Alumni Committee of College
Member – College Research Committee (Till November 19, 2015)
Member – College Internal Quality Assurance Cell (IQAC) (Till November 19, 2015)
Member – College Archives Committee
Member – UGC XIITH Plan Grants Committee 
Member – Generic Committee Allotment Committee
Member - Screening Committee for Professor Application to outside institutions
Member - Screening Committee for Appointing Vice-Principal of the College
Member - Committee for ERP solution for paperless administrative, financial and academic management of the College
Member-Time Table Committee
Member – NIRF Committee
 
Year 2014 – 2015
Teacher-in-Charge – Department of Electronics 
Convener-Research Centre
Convener-AICTE form filling up committee
Convener – Website Committee
Convener – Career Counseling and Placement Cell
Member- Academic Devlopment Committee
Member-Library Committee
Member – Alumni Committee of College
Member – College Research Committee
Member – College Internal Quality Assuarnace Cell (IQAC) 
Member – College Archives Committee
Member – UGC XIITH Plan Grants Committee 
Member - Screening Committee for Appointing Vice-Principal of the College
Member-Time Table Committee
Convener-Admission Committee for Electronics
 
Year 2013 – 2014
Convener – Website Committee
Convener – Career Counseling and Placement Cell
Member – College Archives Committee
Member – Alumni Committee of College
Convener- Committee for Sending Proposal to DU regarding MSME, Govt. of India.
Member – UGC XIITH Plan Grants Committee 
Member – College NAAC Steering Committee 
Member – College Research Committee
Member – College Internal Quality Assuarnace Cell (IQAC) 
 
Year 2012 – 2013
Convener – College Archives Committee
Convener - Prospectus Committee
Convener – Career Counseling and Placement Cell
Member – Website Committee
Member – Alumni Committee of College
Member – College Committee for Antardhvani 2013, University of Delhi
 
Year 2011 – 2012
Convener-Career Counseling and Placement Cell
Member-Admission Committee
Member – Alumni Committee of College
Member – Departmental Technical and Purchase Committee
 
Year 2010 – 2011
Convener – Placement Cell
Member – Gandhi Study Circle, DDU College
Member – Rajiv Gandhi Study Circle, DDU College
Member – Alumni Committee of College
Member – Departmental Technical and Purchase Committee
Member – Lab. Development Committee for Labs in New Block
 
Year 2009 – 2010
Convener – Aryabhatta Science Forum
Member – Gandhi Study Circle, DDU College
Member – Rajiv Gandhi Study Circle, DDU College
Member - Prospectus Committee
Member – Canteen Committee
Member – Committee for purchase of office automation software for college
Member – Committee for renovation of furniture for staff room, principal office and seminar room of college
 
Year 2008 – 2009
Convener - Prospectus Committee
Member –Magazine Committee
Member – Canteen Committee
Member - Placement Cell
Member - Admission Committee
Member - Website Committee
Member – Aryabhatta Science Forum
 
Year 2007 – 2008
Convener - College Prospectus Committee
Co-Convener - Time Table Committee
Treasurer- DDUC Teaching Staff Association
Member - College Placement Cell
Member - Admission Committee
Member - Library Stock Verification Committee
 
Year 2006 – 2007
Convener - College Prospectus Committee
Member - College Placement Cell
Member - Admission Committee
Member - Library Stock Verification Committee
Member - Purchase Committee
Member - Departmental Lab. maintenance Committee
 
Year 2005 - 2006
Member - Student Activity Committee
Member - College Prospectus Committee
Member - College Website Committee
Member - Departmental Purchase Committee
Member - College Infrastructure Development Committee
Member - Proctorial Board
Member - Aryabhatta Science Forum
Member - Library Stock Verification Committee
Member - Admission Committee
Member - Purchase Committee
Treasurer- DDUC Teaching Staff Association
 
Year 2004 - 2005
Member - Technical Library Purchase Committee.
Member - Library Stock Verification Committee 
Member - Departmental Technical Committee 
Member - Departmental Time Table Committee 
Member - Student Activity Committee 
Member - Prospectus Committee 
Member - Website Development Committee
 
Year 2003 - 2004
Member - Technical purchase Committee
Member - Discipline Committee 
Member - Sports Committee  
Areas of Interest / Specialization
Modeling and simulation of sub-100 nm Nanoelectronics Devices:
  • Epitaxial Channel and Drain Engineered MOSFET
  • Dual/ Tripple Material Gate (DMG/ TMG) MOSFET
  • Silicon on Nothing (SON) MOSFET
  • Insulated Shallow Extension (ISE) MOSFET
  • Recessed Channel/ Grooved/ Concave Gate MOSFET 
  • Tunnel FET
  • Optically Controlled FET (OPFET)
  • Mercuric Iodide (HgI2) X-Ray Detectors
  • High Electron Mobility Transistor (HEMT)
Subjects Taught

Post Graduate Level (As Visiting Faculty)

Course

Year

M. Sc Electronics (IVth Semester) - VLSI Circuit Design and Device Modelling – 4.2 (Deptt. Of Electronic Science, University of Delhi South Campus)

 

Jan 2013 – April 2013
Jan 2012 – April 2012
January 2011 – April 2011

M. Sc Electronics (Ist Semester) -  Advance Analog and Digital Electronics - 1.4 - (Deptt. Of Electronic Science, University of Delhi South Campus)

 

July 2012 – December 2012
July 2011 – December 2011
July 2010 – December 2010
July 2009 – December 2009
July 2008 – December 2008
July 2005 – December 2005
July 2004 – December 2004

M. Sc Informatics – Introduction to Communication Systems – IT-13 - (Institute of Informatics & Communication, University of Delhi South Campus)

2005-2006

 
 
Under Graduate Level
 

B. Sc. (H) Electronics IV Semester – Signal and Systems

January  2017 – April 2017
January  2018 – April 2018

B. Sc. (H) Electronics IV Semester – Operational Amplifier

January  2019 – April 2019

B. Sc. (H) Electronics III Semester – Electronic Circuits

July 2016 – November 2016
July 2017 – November 2017
July 2018 – November 2018

B. Sc. (H) Electronics II Semester – Applied Physics

January 2016 – April 2016

B. Sc. (H) Electronics I Semester – Mathematics Foundation for Electronics

July 2015-November 2015

B. Tech Electronics (FYUP) - III Semester – Analog Electronics-I

July 2014-November 2014

B. Tech Electronics (FYUP) – II Semester – Semiconductor Devices

January 2014-April 2014

B. Sc. (H) Electronics III Semester – Analog Electronics-I

July 2013-November 2013
July 2012-November 2012
July 2011-November 2011

B. Sc. (H) Electronics II Semester – Signal and Systems

January 2015-April 2015
January 2013-April 2013
January 2012-April 2012
January 2011-April 2011

B. Sc. (H) Electronics I Semester – Network Analysis

July 2010-November 2010

B. Sc. (H) Electronics I year – Network Analysis and Linear Active circuits

2009-2010
2008-2009
2007-2008
2004-2005
2003-2004
2002-2003

B. Sc. (H) Electronics II year – Operational Amplifier and Analog Computation

2009-2010
2008-2009
2007-2008
2006-2007
2005-2006

B. Sc. (H) Electronics II year – Numerical analysis and FORTRAN programming

2008-2009
2007-2008

B. Sc. (H) Electronics III year – Engineering Drawing

2003-2004

B. Sc. (H) Electronics III year – Power Electronics

2006-2007
2005-2006

B. Sc. (H) Electronics III year – Communication System

2003-2004
2002-2003

B. Sc (H) Computer Science I semester  - Digital Electronics

2006-2007
2005-2006
2004-2005

B. Sc (H) Computer Science II semester  - Analog Electronics

2003-2004

B. Sc (H) Computer Science V semester  - Microprocessor

2004-2005
2003-2004

 

 

Research Guidance

Supervision of awarded Doctoral Thesis

Two

Supervision of Doctoral Thesis, under progress

Five

Supervision of awarded M.Phil dissertations

Three

Supervision of M.Phil dissertations, under progress

Nil

 
Research Guidance/ Supervision - Joint Supervision

Joint Supervision

S. No.

Title

Candidate’s name and Affiliation

Year

Status

  1.  

Modeling and simulation of Nanoscale Dual Material Gate Insulated Shallow Extension Silicon on Nothing MOSFET for Low voltage low power applications

Ms. Vandana Kumari, Research Scholar, UGC-NET (LS)
Department of Electronic Science,
University of Delhi South Campus, New Delhi.

Jan-2010

Awarded

  1.  

Analytical Modeling and Simulation Study of BioFETs for Label Free Electrical Detection of Biomolecules

Mr. Ajay, Research Scholar, UGC-NET-JRF
Department of Electronic Science,
University of Delhi South Campus, New Delhi.

July-2013

Awarded

  1.  

Modeling and Simulation of Steep Subthreshold Emerging Research Devices for Energy Efficient Low Power Sensing Applications

Mr. Avashesh Dubey, UGC-NET
Department of Electronic Science,
University of Delhi South Campus, New Delhi.

January

2015

On-Going

  1.  

Modeling and Simulation of AlGaN/GaN HEMT

Mr. Ajay Vishwakarma
Department of Electronic Science,
University of Delhi South Campus, New Delhi.

August 2017

On-Going

  1.  

Modeling and Simulation of Field Plate HEMT

Ms. Neha, Department of Electronic Science,
University of Delhi South Campus, New Delhi.

August 2017

On-Going

6 Modeling, Simulation and performance comparison of AlGaN and GaN Channel HEMTs
Ms. Anupama
Department of Electronic Science, 
University of Delhi South Campus, New Delhi.
 
August 2019 On-Going
7 Numerical Investigation of Advaned AlGaN/GaN HEMT for high power Applications
Mr. Khushwant Sehra
Department of Electronic Science, 
University of Delhi South Campus, New Delhi.
 
August 2019 On-Going


Supervision of M. Phil dissertation

Name of the Candidate

Title of the Dissertation

University/ Roll. No.

Year/ Status

Ms. Rakhi Narang

A Gate-Induced Drain-Leakage Current Model for Fully Depleted Double-Gate MOSFETS

Reg. No – 605011080014

2009/ Awarded

Ms. Sonia Ahlawat

Modeling and Analysis of Body Potential of  Cylindrical Gate-All-Around Nanowire Transistor

Reg. No -605011080015

2009/ Awarded

Ms. Neha

Microwave Modeling and Parameter extraction method for Quantum Well Laser

Reg. No –C8HR016M1250029

2009/ Awarded

 

At National Level
(Summer Research Fellowship Sponsored by Indian Academy of Sciences (IAS), National Academy of Sciences, India (NASI) & Indian National Science Academy (INSA))

S. No.

Title

Candidate’s name and Affiliation

Duration

Status of Project

1.                    

Computer Aided Analysis, Charecterization, Optimization and Simulation of Bio-Molecules of Field Effect Biosensors

Jagriti Mishra
B. Tech, BITS Meshra
(ENGS1368)

May-July2010

Completed

2.                    

Analytical modeling and Simulation of Short Channel Effects and Quantum-Confinement Effects in Silicon Nanowire MOSFET

 

Gaurav Mahajan
B.E. (Hons.) Electrical and Electronics Engineering
Birla Institute of Technology and Science, Pilani (ENGS2982)

May-July2010

Completed

Currently studying MS in Electrical Engineering at Stanford University, USA

3.                    

Analytical modeling and Simulation of Germanium on Insulator MOSFET for Optical Application

Neha Bhushan
KIIT University, Bhubaneswar(ENGS2269)

May-July2011

TCS Hyderabad

4.                    

Analytical modeling and simulation of Tunnel FET for Sensor application

K V Sasidhar Reddy
NIT, Warangal, (ENGS4147)

May-July2011

Management Trainee

RINL, VIZAG-Steel

5.                    

Modeling and Application of Gate Material Engineered Double Gate Junction-Less Field Effect Transistor for Low-Voltage Low-Power Analog and Digital Circuits

 

Neel Modi
(ENGS7096), Electronics and Communication Engineering
Sardar Vallabhbhai National Institute of Technology (SVNIT), Surat

May-July2013

Completed

6.                    

Logic Circuit design analysis and performance comparison of CMOS with Steep Subthreshold Devices,

Pranav P Nair, (ENGS 5351)
B. Tech III Year, Electrical Engineering, IIT Indore, India

May-July2013

Completed

7.                  

Modeling and Simulation of Nanoscale Multi-Gate MOSFET architectures for Digital and Analog Applications

I. Aravindan, ENGS 3571
B.Tech Electronics and Communication Engineering (III Year)
Amrita Vishwa Vidyapeetham, Coimbatore, Tamil Nadu

May-July2014

Completed

8.                    

Modeling of Tapered Gate Electrode Reconfigurable Double Gate MOSFET incorporating Friging Field Effects

Gokulnath R. ENGS 3099
B.E.III Year, Electrical and Electronics Engineering
Sri Sai Ram Engineering College, Chennai-44

May-July2015

Completed

9.                    

Novel Attributes of Tunnel Field Effect Transistors over conventional FET based devices

Sakshi Gupta, ENGS 6707
Electronics and Communication Engineering
ITM University, Gurgaon, Haryana

May-July2015

Completed

10.                

Impact of Gate Underlap Region on the Electrostatistics of FINFET Architecture using Efficient 3D Analytical Model

Sharmetha K., ENGS 9097
Electronics and Communication Engineering,
K.S.Rangaswamy College of Technology, Namakkal, Tamil Nadu, India

May-July2015

Completed

11.                

Modeling and Simulation of FINFET and its circuit applications

Prabhleen Singh, ENGS1202
B. Tech IIIrd Year, Department of Electronics
Electronics and Communication Engineering
Jaypee Institute of Information Technology, Noida-201307

June-August2016

Completed

12.                

Modeling and Simulation of Channel Engineered Double Gate Junction Less Field Effect Transistor DG-JLFET

Mr. Ayush Kumar, ENGS3866
B-305, Neelkanth Boys Hostel, NIT Hamirpur, Hamirpur 177 005

June-August2016

Completed

13.                

Analysis of GATE Engineered Double Gate Junctionless Field effect Transistor for Optical Detection

Mr. Abhineet Sharan, (ENGS 5560)
B. Tech Electronics and Communication Engineering,
PDPM Indian Institiute of Information Technology
Design and Manufactring, Jabalpur

May-July 2017

Completed

14.                

Analytical Modelling and Simulation Study of Homo and Hetero III-V Semiconductor Based Tunnel Field Transistor (TFET)

Ms. Lakshmi Varshika M,
B. E. Hons. 3rd Year,
Department of Electrical and Electronics
Birla Institute of Technology and Science, Pilani
Hyderabad

May-July 2017

Completed

15.                

Studying Novel attributes of Drain Region Extensions and Source Region Tunnelling in a single device for SoC applications

Ms. Hasti Kasundra, ENGS 6742
Electronics and Communication Engineering
SVNIT, Surat, Gujrat 395007

May-July 2018

Completed

16.                

Investigation of Electrical Characteristics of Multi Gate AlGaN/ GaN HEMT

Khushwant Sehra, ENGS290
M. Tech Electronics and Communication Engineering
University School of Information, Communication & Technology
Guru Gobind Singh Indraprastha University

May-July 2018

Completed

17.                

Analytical Modeling and Simulation of Steep Subthreshold Hono/Heterojunction Tunnel FET and its optical applications

Brahmadutta Dixit, FENGS 118
Electronics and Communication Engineering
Mizoram University, Aizawl, Mizoram 796004

May-July 2018

Completed

18 TCAD Basd Assessment of Advanced AlGaN/GaN HEMT with AlN Cap Layer
Ms Shreyasi Das, ENGS3771
University of Calcutta, Kolkata
 
May-July 2019 Completed
19
Modelling and Simulation based Investigation of Ferroelectric DG-MOSFETs and DG-TFETs for switching applications and circuit design
 
Ms Reshma S Kumar, ENGS3045
Delhi Technological University, New Delhi
 
May-July 2019 Completed
20 Modeling and Simulation Study of Different FET and TFET Architectures for Bio-sensing and Gas-sensing Applications
Ms Shrabasti Mondal, ENGS2999
National Institute of Technology, Durgapur
 
May-July 2019 Completed
21 Modelling and Simulation of Asymmetric Gate AlGaN/GaN HEMT using ADS and TCAD
Ms Amrutamayee Nayak, ENGS4992
National Institute of Science & Technology, Berhampur
 
May-July 2019 Completed
         

At College Level

Under Graduate Students (As Guide):   09

S. No.

Title

Candidate’s name and Affiliation

Year

  1.  

Implementation of a Nanoelectronic Full Adder and Nano-circuit to control millimeter scale walking robot

Sumit Jain, B. Sc. (H) Computer Science- Sixth Semester
Deen Dayal Upadhyaya College, University of Delhi

2007

  1.  

HeRMES: High-Performance Reliable MRAM-Enabled Storage and On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories

Angad Singh, B. Sc. (H) Computer Science- Sixth Semester
Deen Dayal Upadhyaya College, University of Delhi

2007

  1.  

Banked Microarchitectures for Complexity-Effective Superscalar Microprocessors

Gaurav Arora, B. Sc. (H) Computer Science- Sixth Semester
Deen Dayal Upadhyaya College, University of Delhi

2007

  1.  

Handwriting Recognition Using

Artificial Neural Networks

Sagar Rangra, B. Sc. (H) Computer Science- Sixth Semester
Deen Dayal Upadhyaya College, University of Delhi

2008

  1.  

Data And Picture Encryption Using Image Processing

Ankit Bhatia, B. Sc. (H) Computer Science- Sixth Semester
Deen Dayal Upadhyaya College, University of Delhi

2008

  1.  

Pattern Recognition

Preeti Duhan, B. Sc. (H) Computer Science- Sixth Semester
Deen Dayal Upadhyaya College, University of Delhi

2008

  1.  

Expert System Architecture

Garima Arora, B. Sc. (H) Computer Science- Sixth Semester
Deen Dayal Upadhyaya College, University of Delhi

2008

  1.  

Neural Networks

Saarthak Shandilya, B. Sc. (H) Computer Science- Sixth Semester
Deen Dayal Upadhyaya College, University of Delhi

2008

  1.  

Survivability on unbounded networks

Ashish Arora, B. Sc. (H) Computer Science- Sixth Semester
Deen Dayal Upadhyaya College, University of Delhi

2008

 

Publications Profile
Publication Details (as on March 31, 2020)
 
Total 305
International Refereed Journals 112
Full Papers in International Conference Proceedings 108
Full Papers in National Conference Proceedings 028
Abstracts in International Conferences 053
Abstracts in National Conferences 004
 
ORCID Webpage              : http://orcid.org/0000-0002-9368-4194             

Scopus Webpage             : http://www.scopus.com/authid/detail.url?authorId=35480023200

ResearcherID-Thomson Reuters : http://www.researcherid.com/rid/K-3863-2015

Invited Talk Delivered:

  1. “Applications of Quantum Mechanics in Nanoscale Electronics”,  Second National Workshop On Quantum Mechanics: Theory and Application Organized By FiDAS, Deen Dayal Upadhyaya College, University of Delhi, Sponsored By CSIR, Govt of India Supported By IEEE EDS Delhi Chapter, New Delhi and The National Academy of Sciences, India, - Delhi Chapter held during October 22-23, 2010 
  2. “Applications of Quantum Mechanics in Nanoscale Electronics”,  Second National Workshop On Quantum Mechanics: Theory and Application Organized By FiDAS, Deen Dayal Upadhyaya College, University of Delhi, Sponsored By CSIR, Govt of India Supported By IEEE EDS Delhi Chapter, New Delhi and The National Academy of Sciences, India, - Delhi Chapter held during October 29-30, 2010.
  3. “Applications of Quantum Mechanics in Nanoscale Electronics: Size Quantization Effect”, Physics Workshop organized by Kendriya Vidyalaya, R. K. Puram, Sector-2, New Delhi from December 24, 2010 to January 02, 2011
  4. “Quantum Mechanics for Nanoelectronics” in Continuing Education Program (CEP) on “Nanoelectronics” from 17th – 21st January 2011 organized by Solid State Physics Laboratory, (laboratory under the Defence Research & Development Organization (DRDO), Govt. of India)  
  5. “Tunnel Field Effect Transistor – A Biomolecule Sensor”, Twenty Third Meeting of Indian Academy of Sciences, Bangalore held during 13th - 14th, July 2012.
  6. Delievered Invited talk on “Information Handling”on May 24, 2013 during First Orientation Programme for Teachers of the Foundation Course –    Information Technology organized by CPDHE-ILLL, University of Delhi during May 23-25, 2013
  7. Delievered Invited talk on “Information Handling” on May 29, 2013 during Second Orientation Programme for Teachers of the Foundation Course –    Information Technology organized by CPDHE-ILLL, University of Delhi during May 28-30, 2013
  8. Delievered Invited talk on “Information Handling” on June 05, 2013 during Third Orientation Programme for Teachers of the Foundation Course –    Information Technology organized by CPDHE-ILLL, University of Delhi during June 04-06 , 2013
  9. Delievered Invited talk on “Information Handling” on June 13, 2013 during Fourth Orientation Programme for Teachers of the Foundation Course –    Information Technology organized by CPDHE-ILLL, University of Delhi during June 12-14, 2013
  10. Delievered Invited talk on “Information Handling” on June 29, 2013 during Orientation Programme (OR-74) organized by CPDHE, University of Delhi during June 20, 2013  – July 17, 2013
  11. Delivered Invited Talk on " Information Technology" on July 17, 2013 during Master Class for First Year Students of different colleges of DU admitted under FYUP 2013 organized by CPDHE-ILLL, University of Delhi. The Master Classes for the Foundation Courses will bring 40 first year students from a few colleges  for an Introductory session on 15 July (getting to know  the university), to be followed by two days of intensive classes on 16 and 17 July for  seven  Foundation Courses. 
  12. Delivered Invited talk on “Information Handling” on July 27, 2013 during Fifth Orientation Programme for Teachers of the Foundation Course – Information Technology organized by CPDHE-ILLL, University of Delhi during July 26, 2013 - July 29, 2013
  13. Delivered Invited talk on “Information Handling” on January 19, 2014 during Sixth Orientation Programme for Teachers of the Foundation Course – Information Technology organized by CPDHE-ILLL, University of Delhi during January 18 , 2014 - January 19, 2014
  14. Delivered Invited talk on ELECTRONICS: THE SECOND SUNRISE at Three Days Workshop for PGT organized by Bal Bharti Public School (Pitampura) Training Centre, May 18-20, 2015 (Duration of the Talk: 3 Hours)
  15. Delivered Invited talk on “Development and Career Opportunities in Photonics” on Einstein Day celebrated at Bal Bharti Public School (Dwarka) on July 27, 2015 (Duration of the Talk: 1 Hour)
  16. Delivered Invited Talk on “Impact of Dielectric Pocket on Different Gate Geometry MOSFET Architectures for Improved Analog and Digital Performance: Modeling and Simulation” in 2nd International Conference on Science, Technology and Management, Delhi University, Conference Centre, New Delhi on September 27, 2015 (Duration of the Talk: 30 Min). http://www.conferenceworld.in/Conference.php?cID=16&task=conference-editorial-board 
  17. Delivered Invited Talk on “Tunnel Field Effect Transistor and its Application as Highly Sensitive and Fast Biosensor” in National Conference on Recent Advances in Material& Field Theory (NCRAMFT-2K15) held during December 28-29, 2015 at Bhagwan Parshuram Institute of Technology, PSP Area-4, Sector-17, Rohini Delhi. ISBN: 978-93-5254-054-9
  18. Delivered Invited Talk on “Einstein and His Contributions & Career Opportunities in Photonics and Challenges in Electronic Devices” at INSPIRE Camp held during February 02, 2016 at Rajdhani College, University of Delhi (Duration 1 Hour)
  19. Delieverd invited lecture on Applications of QM in Nanoelectronics in Third Workshop On “Quantum Mechanics: Theory and Application” during March 13-14, 2016 in Deen Dayal Upadhyaya College, University of Delhi, New Delhi organized jointly by Silizium-Electronics Society, Deen Dayal Upadhyaya College, The National Academy of Sciences, India (NASI) -Delhi Chapter and IEEE Electron Device Society-(Delhi Chapter).
  20. Delievered IEEE Disninguished Lecture on “Tunnel Field Effect Transistor and its Application as Highly Sensitive and Fast Biosensor” at ED University of Calcutta Student Branch Chapter, Calcutta, India on September 22, 2016.
  21. Delievered IEEE Disninguished Lecture on “Dielectric Pocket MOSFET: A Novel Device Architecture” at ED Vellore Institute of Technology - Chennai Student Branch Chapter, Chennai, India on October 14, 2016.
  22. Delievered IEEE Disninguished Lecture on “Modeling and Simulation of Tunnel Field Effect Transistor as a Biosensor” at ED Vellore Institute of Technology Student Branch Chapter, Vellore, Tamil Nadu, India on October 15, 2016.
  23. Deleivered IEEE Disninguished Lecture on Modeling and Simulation of Tunnel Field Effect Transistor as a Biosensor at one day workshop on compact modeling (including device simulation) at IIT Kanpur on 3rd March, 2017 organized by ED Uttar Pradesh Section - Kanpur Chapter Kanpur, Uttar Pradesh, India
  24. Deleivered IEEE Disninguished Lecture on Dielectric Pocket MOSFET: A Novel Device Architecture at 7th IEEE ED Mini-Colloquim ON Quantum Devices held at March 7, 2017 at National Institute of Science and Technology, Palur Hills, Berhampur, Odisha, India – 761008
  25. Delievered invited talk on Application of Tunnel Field Effect Transistor as a Biosensor at 2nd  International Conference “2017 Devices for Integrated Circuit (DevIC)”, held at Kalyani Government Engineering College from March 23-24, 2017, organized by IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC, technically co-sponsored by IEEE EDS Kolkata Chapter.
  26. On March 25, 2017, delievered IEEE Distinguished Lecture on Embedded Insulator based Novel Nanoscaled Novel MOSFET Structures at Meghnad Saha Institute of Technology, Kolkata organized by ED Meghnad Saha Institute of Technology Student Branch Chapter, Kolkata, India.
  27. On April 14, 2017 delievered IEEE Distinguished Lecture on Fundamental Insights into Channel and Gate Engineered Double Gate Junction-Less Transistor for Low-Voltage Low-Power Analog and Digital Circuits at DAIICT organized by ED/SSC Gujarat, India
  28. On May 12, 2017 delivered IEEE Distinguished Lecture on Fundamental Insights into Channel and Gate Engineered Double Gate Junction-Less Transistor for Low-Voltage Low-Power Analog and Digital Circuits at Muffakham Jah College of Engineering and Technology (MJCET), Banjara Hills, Hyderabad, AP. 500034
  29. On May 12, 2017 delivered IEEE Distinguished Lecture on Impact of Dielectric Pocket on Different Gate Geometry MOSFET Architectures for Improved Analog and Digital Performance at  Vasavi College of Engineering, Banjara Hills, Hyderabad, AP. 500034
  30. On June 23, 2017 delivered IEEE Distinguished Lecture on Modeling and Simulation of Tunnel Field Effect Transistor as a Biosensor at CSIR-CEERI, Pilani, India.
  31. On June 24, 2017 delivered IEEE Distinguished Lecture on Fundamental Insights into Channel and Gate Engineered Double Gate Junction-Less Transistor for Low-Voltage Low-Power Analog and Digital Circuits at Poornima University, ISI-2, RIICO Institutional Area, Sitapura, Jaipur (Rajasthan) 302022.
  32. On July 02, 2017 delivered Invited talk on Best Practices in Writing Journal/Conference papers in Electron Devices in CAS/EDS Research Forum Organised by IEEE Joint chapter of CAS/ED Societies, Hyderabad Section
  33. On July 02, 2017 delivered Invited talk on Research opportunities in Electron Devices in CAS/EDS Research Forum Organised by IEEE Joint chapter of CAS/ED Societies, Hyderabad Section
  34. On July 21, 2017 delivered Invited talk on Modeling and simulation of Gate Electrode Engineered Double Gate Junctionless Transistor in IEEE MQ organized by Heritage Institute of Technology, IEEE EDS Student Branch Chapter.
  35. On August 29, 2017 delivered IEEE Distinguished Lecture on Research opportunities in Electron Devices at Department of Electronics and Communication, Model Institute of Engineering & Technology (MIET), Jammu.
  36. On August 29, 2017 delivered IEEE Distinguished Lecture on Best Practices in Writing IEEE Conference / Journal Papers at Department of Electronics and Communication, Model Institute of Engineering & Technology (MIET), Jammu
  37. On October 03, 2018 deleivered Technical Talk on Emerging Transistor Designs for Next Generation FPGAs in Fifth Hands on Workshop On VHDL Programming & Digital Circuit Designing with Implementation on FPGA organized under the Aegis of DBT Star College Program (Electronics) in collaboration with CoreEL Technologies (I) Pvt. Ltd. at Deen Dayal Upadhyaya College, University of Delhi, New Delhi 110078.
  38. On October 20, 2018 delivered IEEE Distinguished Lecture on Fundamental Insights into Channel and Gate Engineered Double Gate Junction-Less Transistor for Low-Voltage Low-Power Circuits at Malaviya National Institute of Technology Jaipur under IEEE EDS of PU and IEEE Rajasthan Subsec-tion.
  39. On November 03, 2018 deleivered IEEE Distinguished Lecture on Novel Junction-Less (JL) Transistor Designs in IEEE-EDS Mini Colloquium (MQ) on Recent Trends in Microelectronics & VLSI Design held at Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam, India organized by IEEE-ED NIT Silchar, Student Branch Chapter
  40. On November 24, 2018 delivered Invited talk on Modeling and Simulation of Tunnel Field Effect Transistor as a Biosensor at 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), The Pride Hotel, Kolkata, India during November 24-25, 2018 organized by IEEE EDS Kolkata Chapter.
  41. On November 24, 2018 deleivered IEEE Distinguished Lecture on Recent Advances in Tunnel Field Effect Transistor for Sensing Applications at Netaji Subhash Engineering College, Techno City, Garia, Kolkata – 700152.
  42. On December 21, 2018 delievered four invited talks in Five-Day Short-Term Course (STC)On Recent Trends in Nano-Electronics and VLSI (RTNV) organized by Department of Electronics and Communication Engineering, National Institute of Technology (NIT) Kuruskshetra, Haryana, India during December 18-22, 2018 (Lecture 1 - About EDS Society, Review of Si-MOSFET - Bulk, GAA, DG and Silicon on Nothing MOSFET (Duration 1 hr 15 min); Lecture 2 - Dielectric Pocket MOSFET, Junctionless MOSFET (Duration 1 hr 15 min); Lecture 3 - Operation of Tunnel FET; Advance TFET architectures; Application of TFET as Biosensor (Duration 1 hr 15 min) and Lecture 4 - Basic operation of AlGaN-HEMT; Types of HEMT architectures; Field Plate HEMT for High Voltage Application (Duration 1 hr 15 min)
  43. On August 20, 2019 delivered IEEE Distinguished Lecture on Modeling and Simulation of Tunnel Field Effect Transistor as a Biosensor at Indira Gandhi Delhi Technical University for Women (IGDTUW), New Delhi, India.

Other publications (Edited works, Book reviews, Festschrift volumes, etc.)

  1. Member - Editorial Board - Proceedings of 16th Asia Pacific Microwave Conference 2004, Department of Electronic Science, University of Delhi, Allied Publishers Pvt. Ltd. 2004, ISBN 81-7764-722-9.
  2. Proceeding Editor - National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2006) from 22nd March – 25th March 2006, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India, ISBN: 81-8424-026-0
  3. E-Proceeding Editor - National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2008) from 26th September – 28th September 2008, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India
  4. Editor – Proceeding of the International Symposium on Microwave and Optical Technology (ISMOT)-2009, December 16-19, 2009.
  5. Proceeding Editor - Third National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2010) held during January 30-31, 2010, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India, sponsored By University Grants Commission (UGC), Govt. of India

Book

  • “Information Technology”, D. V. Singh, Shailender Kumar, Neeraj Tyagi, Pankaj Tyagi, Sanjeev Singh, Manoj Saxena and Ranjan Kumar, Universities Press, ISBN 9788173719004 (2013)

Book Chapter

  • MOSFET Modeling, R. S. Gupta, Mridula Gupta and Manoj Saxena, Encyclopedia of RF and Microwave Engineering, John-Wiley & Sons, Inc. New Jersey, USA, March 2005, pp. 3278-3317, ISBN: 0-471-27053-9.

Research papers published in Refereed/Peer Reviewed Journals

Papers published in International Journals: -

  1. Physics Based Analytical Modeling of Potential and Electrical Field Distribution in Dual Material Gate (DMG)-MOSFET for Improved Hot Electron Effect and Carrier Transport Efficiency, Manoj Saxena, Subhasis Haldar, Mridula Gupta, and R. S. Gupta, IEEE Transaction on Electron Devices, Vol. 49, No. 11, pp. 1928-1938, November 2002. DOI: 10.1109/TED.2002.804701 ISSN : 0018-9383
  2. Physics Based Modeling and Simulation of Dual Material Gate Stack (DUMGAS) MOSFET, Manoj Saxena, Subhasis Haldar, Mridula Gupta and R. S. Gupta, IEE Electronics Letter, 9th January, Vol. 39, No.1, pp-155-157, January 2003. Online ISSN 1350-911X, Print ISSN 0013-5194
  3. Modeling and simulation of asymmetric gate stack (ASYMGAS)-MOSFET, Manoj Saxena, Subhasis Haldar, Mridula Gupta and R. S. Gupta, Solid State Electronics, Vol. 47, pp. 2131-2134, 2003. ISSN: 0038-1101
  4. Design considerations for novel device architecture: Hetro -Material Double-Gate (HEM-DG) MOSFET with sub –100 nm gate length Manoj Saxena, Subhasis Haldar, Mridula Gupta and R.S. Gupta, Solid State Electronics Vol. 48, pp. 1169-1174, 2004. ISSN: 0038-1101
  5. Optimization of Gate stack MOSFETs with Quantization effects, Tina Mangla, Amit Sehgal, Manoj Saxena, Subhasis Haldar, Mridula Gupta and R. S. Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol.4, No.3, pp. 228-239, September 2004. ISSN 1598-1657 (Print) ISSN 2233-4866 (Online)
  6. Two-Dimensional Analytical Modeling and Simulation of Retrograde doped HMG MOSFET, Kirti Goel, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Journal of High Speed Electronics and Systems, Vol.14, No.3, pp.676-683, September 2004. Print ISSN: 0129-1564, Online ISSN: 1793-6438
  7. Two-Dimensional Analytical Threshold Voltage Model for Dual Material Gate (DMG) Epi-MOSFET, Kirti Goel, Manoj Saxena, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol.52, No.1, pp.23-29, January 2005. ISSN : 0018-9383
  8. Physics-based algorithm implementation for characterization of gate dielectric engineered MOSFETs including Quantization effects, Tina Mangla, Amit Sehgal, Manoj Saxena, Subhasis Haldar, Mridula Gupta and R. S. Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol.5, No.3, pp. 159-167, September 2005. ISSN 1598-1657 (Print) ISSN 2233-4866 (Online)
  9. Modeling and Simulation of Stacked Gate Oxide (STGO) Architecture in Silicon-On-Nothing (SON) MOSFET Poonam Kasturi, Manoj Saxena and R.S. Gupta, Solid State Electronics, Vol. 49, No. 10, pp. 1639-1648,October 2005. ISSN: 0038-1101
  10. Modeling and Simulation of a Nanoscale Three Region Tri MAterial Gate Stack (TRIMGAS) MOSFET for Improved Carrier Transport Efficiency and Reduced Hot Electron Effects, IEEE Transactions on Electron Devices, Kirti Goel, Manoj Saxena, Mridula Gupta and R. S. Gupta, Vol. 53, No. 7, pp. 1623-1633, July 2006. ISSN : 0018-9383
  11. Two-Dimensional Analysis and Simulation for Gate Stack Silicon-On-Nothing MOSFET (GAS-SON MOSFET), Poonam Kasturi, Manoj Saxena, R.S. Gupta, International Journal of Microwave and Optical Technology Letter (IJMOT), Vol. 1, No. 2, pp. 417-421, August 2006. ISSN 1553-0396
  12. Performance Investigation of 50nm Insulated Shallow Extension Gate Stack (ISEGaS) MOSFET for Mixed Mode Applications, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Transactions on Electron Devices, Vol. 54, No.2, pp. 365-368, February 2007. ISSN : 0018-9383
  13. Unified model for physics based modeling of a new device architecture:Triple Material Gate Oxide Stack Epitaxial Channel Profile (TRIMGASEpi) MOSFET, Kirti Goel, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science and Technology, vol. 22, pp. 435-446, 2007. 
  14. Hot carrier reliability and analog performance investigation of DMG-ISEGaS MOSFET Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, IEEE Transactions on Electron Devices, Vol. 54, No. 9, pp. 2556-2561, September 2007. ISSN : 0018-9383
  15. Unified Subthreshold Model for Channel Engineered Sub-100nm Advanced MOSFET Structures Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, IEEE Transactions on Electron Devices Vol. 54, No. 9, pp. 2475-2486, September 2007. ISSN : 0018-9383
  16. Two-Dimensional Analytical Model to Characterize Novel MOSFET Architecture: Insulated Shallow Extension (ISE) MOSFET, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta Semiconductor Science Technology, Vol.22, pp. 952-962, 2007. Online ISSN: 1361-6641, Print ISSN: 0268-1242
  17. Lateral channel engineered- hetero material insulated shallow extension gate stack (HMISEGAS) MOSFET structure: high performance RF solution for MOS technology Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta Semiconductor Science Technology, Vol. 22, No.10, pp. 1097-1103, 2007. Online ISSN: 1361-6641, Print ISSN: 0268-1242
  18. Dual Material Double Layer Gate Stack SON MOSFET: A Novel Architecture for enhanced analog performance – Part I Impact of Gate Metal Workfunction Engineering, Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol. 55, No. 1, pp. 372-381, January 2008. ISSN : 0018-9383
  19. Dual Material Double Layer Gate Stack SON MOSFET: A Novel Architecture for enhanced analog performance – Part II Impact of Gate Dielectric Material Engineering, Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol. 55, No. 1, pp. 382-387, January 2008. ISSN : 0018-9383
  20. Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET For ULSI, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Microelectronic Engineering, Vol. 85, No. 3, pp. 566-576, March 2008. ISSN: 0167-9317
  21. Two-dimensional analytical sub-threshold model of multi-layered gate dielectric recessed channel (MLaG-RC) nanoscale MOSFET, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science Technology Vol.23, 045006 (10pp) 2008. Online ISSN: 1361-6641, Print ISSN: 0268-1242
  22. Intermodulation Distortion and Linearity Performance Assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC Design, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Superlattices and Microstructures, Vol.44, pp. 143-152, 2008. ISSN: 0749-6036
  23. On-state and RF performance investigation of sub-50nm L-DUMGAC MOSFET design for high-speed logic and switching applications, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Semiconductor Science Technology, 23 095009 (8pp), 2008. Online ISSN: 1361-6641, Print ISSN: 0268-1242
  24. TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its Multi-Layered Gate Architecture: Part-I: Hot Carrier Reliability Evaluation, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, IEEE Transactions on Electron Devices, Vol. 55, No. 10, pp. 2602-2613, October 2008. ISSN : 0018-9383
  25. A TCAD study of Sub-100 nm Advance Gate Electrode Workfunction Engineered SON-MOSFET, R. S. Gupta, Manoj Saxena and Poonam Kasturi, International Journal of Microwave and Optical Technology Letter (IJMOT), Vol. 3, No. 3, pp. 190-195, July 2008. ISSN: 1553-0396
  26. Investigation of Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel (MLGEWE-RC) Sub-50nm MOSFET: A Novel Design, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Journal of Numerical Modeling: Electronic Networks, Devices and Fields, Wiley, Vol. 22, No. 3, pp. 259-278, March/ April 2009. ISSN: 1099-1204
  27. Two-dimensional threshold voltage model and design considerations for gate electrode workfunction engineered recessed channel (GEWE-RC) nanoscale MOSFET: part I, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Semiconductor Science Technology, Vol. 24, No 6, 065005 (10pp), (June 2009). Online ISSN: 1361-6641, Print ISSN: 0268-1242
  28. Two Dimensional Simulation and Analytical Modeling of a Novel ISE MOSFET with Gate Stack Configuration, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, Mridula Gupta and R. S. Gupta, Microelectronic Engineering, Volume 86, Issue 10, Pages 2005-2014, October 2009. ISSN: 0167-9317
  29. TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Superlattices and Microstructures, Volume 46, Issue 4, Pages 645-655, October 2009. ISSN: 0749-6036
  30. Hot-Carrier Reliability Monitoring of DMG ISE SON MOSFET for improved Performance, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Microwave and Optical Technology Letter, pp. 652-657, Vol. 52, No. 3, March 2010. ISSN: 1098-2760
  31. Design Considerations and Impact of Technological papramteric variations on RF/Microwave performance of GEWE-RC MOSFET, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Microwave and Optical Technology Letter, pp. 770-775, Vol. 52, No. 3, March 2010. ISSN: 1098-2760
  32. Effect of Temperature and Gate Stack on the Linearity and Analog Performance of Double Gate Tunnel FET, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, Trends in Network and Communications, Proceedings of International Conferences, NeCOM, WeST, WiMoN 2011, Chennai, India, July 15-17, 2011, Edited by David C. Wyld, Michal Wozniak, Nabendu Chaki, Natarajan Meghanathan and Dhinaharan Nagamalai, Communications in Computer and Information Science, Volume 197, Part 2, 466-475, 2011. DOI: 10.1007/978-3-642-24043-0, Print ISBN: 978-3-642-24042-3, Online ISBN: 978-3-642-24043-0
  33. Channel Material Engineered Nanoscale Cylindrical Surrounding Gate MOSFET with Interface Fixed Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, Trends in Network and Communications, Proceedings of International Conferences, NeCOM, WeST, WiMoN 2011, Chennai, India, July 15-17, 2011, Edited by David C. Wyld, Michal Wozniak, Nabendu Chaki, Natarajan Meghanathan and Dhinaharan Nagamalai, Communications in Computer and Information Science, Volume 197, Part 2, 476-485, 2011. DOI: 10.1007/978-3-642-24043-0, Print ISBN: 978-3-642-24042-3, Online ISBN: 978-3-642-24043-0
  34. Impact of Interface Fixed Charges on the Performance of the Channel Material Engineered Cylindrical Nanowire MOSFET, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, International journal of VLSI design & Communication Systems ( VLSICS ), Vol. 2, No. 3, pp. 225-241, September 2011. ISSN 0976-1357 (Online) 0976-1572 (Print)
  35. Linearity and Analog Performance analysis of Double Gate Tunnel FET: Effect Temperature and Gate Stack, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, International journal of VLSI design & Communication Systems ( VLSICS ), Vol. 2, No. 3, pp. 185-200, September 2011. ISSN 0976-1357 (Online) 0976-1572 (Print)
  36. Fabrication and Time Degradation study of Mercuric Iodide (Red) Single Crystal X-Ray Detector, Kulvinder Singh, Manoj Saxena, J. Nano- Electron. Phys.3 (2011) No. 1, pp. 802-807, 2011. ISSN:2077-6772 (Print); 2306-4277 (Online)
  37. High Sensitivity Photodetector Using Si/Ge/GaAs Metal Semiconductor Field Effect Transistor (MESFET), Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, International Conference on Light :Optics 2011: Phenomenon, Materials, Devices and Charecterization,  Kerala, (India), 23–25 May 2011, AIP Conference Proceedings Volume 1391, pp. 232-234. ISBN: 978-0-7354-0960-6 http://scitation.aip.org/content/aip/proceeding/aipcp/10.1063/1.3646835 
  38. Dielectric Modulated Tunnel Field Effect Transistor - A Bio molecule Sensor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, IEEE Electron Device Letter, Vol. 33, No. 2, pp.266-268 , February 2012. ISSN: 0741-3106
  39. Temperature Dependent Drain Current Model for Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET For Wide Operating Temperature Range, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Microelectronics Reliability, Vol. 52, pp. 974-983, June 2012. ISSN: 0026-2714
  40. Effect of localized charges on Nanoscale Cylindrical Surrounding Gate MOSFET: Analog performance and Linearity Analysis, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Microelectronics Reliability, Vol. 52, pp. 989-994, June 2012. ISSN: 0026-2714
  41. Two Dimensional Analytical Subthreshold Model of Nanoscale Cylindrical Surrounding Gate MOSFET Including Impact of Localised Charges, Rajni Gautam, Manoj Saxena, Mridula Gupta and R. S. Gupta, Journal of Computational and Theoretical Nanoscience (CTN), Vol. 9, No.4, pp. 602-610, April 2012. ISSN: 1546-1955 (Print): EISSN: 1546-1963 (Online)
  42. Simulation Study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for High Temperature Applications, Vandana Kumai, Manoj Saxena, R. S. Gupta and Mridula Gupta, Microelectronics Reliability, Volume 52, Issue 8, Pages 1610-1612,August 2012. ISSN: 0026-2714
  43. Immunity Against Temperature Variability and Bias Point Invariability in Double Gate Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Microelectronics Reliability, Volume 52, Issue 8, Pages 1617-1620, August 2012. ISSN: 0026-2714
  44. Two Dimensional Analytical Drain Current Model for Double Gate MOSFET Incorporating Dielectric Pocket (DP-DG), Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Electron Devices, Vol. 59, No. 10, pp. 2567-2574, October 2012. ISSN : 0018-9383
  45. A Dielectric Modulated Tunnel FET based Biosensor for Label Free Detection: Analytical Modeling Study and Sensitivity Analysis, Rakhi Narang, K. V. Sasidhar Reddy, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Electron Devices, Vol. 59, No. 10, pp. 2809-2817, October 2012. ISSN : 0018-9383
  46. Stability Study on Ceramic Mercuric Iodide (Red) X-Ray Sensor, Kulvinder Singh and Manoj Saxena, Proc. SPIE  8549, 16th International Workshop on Physics of Semiconductor Devices, 854910 (October 15, 2012);   doi: 10.1117/12.924240. Proceedings of SPIE 0277-786X, V.8549 ISSN: 0277-786X, ISBN: 9780819493002
  47. An Analytical Modeling Approach for a Gate All Around (GAA) Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Proc. SPIE  8549, 16th International Workshop on Physics of Semiconductor Devices, 854906 (October 15, 2012);   doi: 10.1117/12.925534  Proceedings of SPIE 0277-786X, V.8549 ISSN: 0277-786X, ISBN: 9780819493002
  48. Digital Circuit Analysis of Insulated Shallow Extension Silicon On Void (ISESOV) FET for Low Voltage Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Proc. SPIE  8549, 16th International Workshop on Physics of Semiconductor Devices, 854905 (October 15, 2012);   doi: 10.1117/12.925533. Proceedings of SPIE 0277-786X, V.8549 ISSN: 0277-786X, ISBN: 9780819493002
  49. Numerical Model of Gate All Around MOSFET With Vacuum Gate Dielectric For Biomolecule Detection, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Electron Device Letter, Vol. 33, No. 12, pp. 1756-1758, December 2012. ISSN: 0741-3106
  50. Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol.12, No.4, pp. 482-491, December, 2012. ISSN 1598-1657 (Print) ISSN 2233-4866 (Online)
  51. Numerical Analysis of Localised Charges Impact on the Static and Dynamic Performance of Nanoscale Cylindrical Surrounding Gate MOSFET Based CMOS Inverter, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Microelectronics Reliability, pp. 236-244, 2013. ISSN: 0026-2714
  52. Analog and Digital Performance Assessment of Empty Space in Double Gate (ESDG) MOSFET: A Novel Device Architecture, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Computational and Theoretical Nanoscience, Volume 10, Number 2, pp. 389-398, February 2013. ISSN: 1546-1955 (Print): EISSN: 1546-1963 (Online)
  53. Hot Carrier Reliability of Gate All Around MOSFET for RF/Microwave Applications, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Device and Materials Reliability, Vol. 13, No. 1, pp. 245-250, March 2013. ISSN: 1530-4388. 
  54. Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol. 13, No. 2, pp. 127-138, April 2013. ISSN 1598-1657 (Print) ISSN 2233-4866 (Online)
  55. Device and Circuit Level Performance Comparison of Tunnel FET Architectures and Impact of Heterogeneous Gate Dielectric”, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol. 13, No.3, pp. 224-236, June 2013. ISSN 1598-1657 (Print) ISSN 2233-4866 (Online)
  56. Analytical Model for Double-Gate Tunneling Field-Effect Transistor (DG-TFET) using carrier concentration approach, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Computational and Theoretical Nanoscience (JCTN), Volume 10, Number 5 (May 2013) pp.1202-1208 (2013). ISSN: 1546-1955 (Print): EISSN: 1546-1963 (Online)
  57. Circuit Level Implementation for Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET: A Novel Device Architecture, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IETE Journal of Research, Volume 59, Issue 4, pp. 404-409, 2013. ISSN 0377-2063 (Print), 0974-780X (Online)
  58. Gate All Around MOSFET With Vacuum Gate Dielectric for Improved Hot Carrier Reliability and RF Performance, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Electron Devices, Vol. 60, No. 6, pp. 1820-1827, June 2013. ISSN : 0018-9383
  59. Comparative Study of Silicon On Nothing and III-V On Nothing Architecture for High Speed and Low Power Analog and RF/Digital Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Nanotechnology, Vol. 12, No. 6, pp.978-984, November 2013. ISSN: 1536-125X
  60. Impact of Temperature variations on the Device and Circuit Performance of Tunnel FET: A Simulation Study, IEEE Transactions on Nanotechnology, Rakhi Narang, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Nanotechnology, Vol. 12, No. 6, pp.951-957, November 2013. ISSN: 1536-125X
  61. Gate All Around MOSFET with Catalytic Metal gate for Gas Sensing Applications, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, IEEE Transactions on Nanotechnology, Vol. 12, No. 6, pp.939-944, November 2013. ISSN: 1536-125X
  62. Drain current model for a gate all around (GAA) p–n–p–n tunnel FET, Rakhi Narang , Manoj Saxena , R.S. Gupta, Mridula Gupta, Microelectronics Journal, Volume 44, Issue 6, pp. 479–488, June 2013. ISSN: 0026-2692
  63. Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol. 13, No.5,pp. 500-510, October 2013. ISSN 1598-1657 (Print) ISSN 2233-4866 (Online)
  64. Performance Investigation of Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET for Low Voltage Digital Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Journal of Semiconductor Science and Technology (JSTS), Vol. 13, No.6,pp. 622-634, December 2013. ISSN 1598-1657 (Print) ISSN 2233-4866 (Online)
  65. Impact of Insulating Layers on Single and Double Gate MOSFET for Improved Short Channel Effect and Hot Carrier Reliability  Vandana Kumari , Manoj Saxena, R. S. Gupta and Mridula Gupta, Invertis Journal of Science and Technology, Vol. 6, no.4, pp. 211-216, 2013. p-ISSN: 0973-8940, e-ISSN: 2454-762X
  66.  Performance Investigation of Silicon Nanowire Tunnel FET for Analog and Digital Applications, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, Invertis Journal of Science and Technology, Vol. 6, No. 4, pp. 254-259, 2013. p-ISSN: 0973-8940, e-ISSN: 2454-762X
  67. Temperature Dependent Subthreshold Model of Long Channel GAA MOSFET Including Localized Charges to Study Variations in its Temperature Sensitivity, Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, Microelectronics Reliability, 54 ( 1 ) pp. 37 – 43, 2014. ISSN: 0026-2714
  68. Analytical Modeling of Dielectric Pocket Double Gate (DP-DG) MOSFET Incorporating Hot Carrier Induced Interface Charges, Vandana Kumari, Manoj Saxena, R.S. Gupta, and Mridula Gupta, IEEE Transactions on Device and Material Reliability, Vol. 14, no.1, pp. 390-399, 2014. ISSN: 1530-4388. 
  69. Investigation of Electrostatic Integrity of Nanoscale Dual Material Gate Dielectric Pocket Silicon On Void (DMGDPSOV) MOSFET for Improved Device Scalability, Vandana Kumari, Manoj Saxena, R.S. Gupta, and Mridula Gupta, IEEE Trans. On Nanotechnology, Vol. 13, no.4, pp. 667-675, 2014. ISSN: 1536-125X
  70. Modeling and simulation of Double Gate Junctionless Transistor considering fringing field effects, Vandana Kumari, Neel Modi, Manoj Saxena and Midula Gupta, Solid State Electronics, Vol. 107, pp. 20-29, 2015. ISSN: 0038-1101
  71. Comparative Analysis of Dielectric-Modulated FET and TFET-Based Biosensor Rakhi Narang, Manoj Saxena and Mridula Gupta, IEEE Transactions on Nanotechnology Vol. 14, no. 3, pp.427-435, May 2015. ISSN: 1536-125X
  72. Theoretical Investigation of Dual Material Junction-Less Double Gate (DM-JL-DG) Transistor for Analog and Digital, Vandana Kumari, Neel Modi, Manoj Saxena and Mridula Gupta, IEEE Trans. On Electron Devices, Vol. 62, No. 7, pp. 2098-2105, July 2015. ISSN : 0018-9383
  73. Investigation of Dielectric Modulated (DM) Double Gate (DG) Junctionless MOSFETs for Application as a Biosensors, Ajay Singh, Rakhi Narang, Manoj Saxena, and Mridula Gupta, Superlattices and Microstructures, Vol 85, pp. 557-572, 2015. ISSN: 0749-6036
  74. Drain Current Model of a Four-Gate Dielectric Modulated MOSFET for Application as a Biosensor, Ajay Singh, Rakhi Narang, Manoj Saxena, and Mridula Gupta, IEEE Trans. On Electron Devices, Vol. 62, No.8, pp. 2636-2644, August 2015. ISSN : 0018-9383
  75. Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET, Vandana Kumari, Manoj Saxena and Mridula Gupta, Journal of Nano Research, Vol. 36, pp.51-63, 2015. ISBN-13:978-3-03835-885-5
  76. Drain Current Model for Hetero-Dielectric based TFET Architectures: Accumulation to Inversion Mode Analysis, Upasana, Rakhi Narang, Manoj Saxena, and Mridula Gupta, Journal of Nano Research, Vol. 36, pp.31-43, 2015. ISBN-13:978-3-03835-885-5
  77. Modeling and TCAD Assessment for Gate Material and Gate Dielectric Engineered TFET Architectures: Circuit-Level Investigation for Digital Applications, Upasana, Rakhi Narang, Manoj Saxena, and Mridula Gupta, IEEE Trans. On Electron Devices, Vol. 62, Issue: 10, pp. 3348 - 3356, 2015. ISSN : 0018-9383
  78. Nanoscale-RingFET: An Analytical Drain Current Model Including SCE’s, Sachin Kumar, Vandana Kumari, Sanjeev Singh, Manoj Saxena, Mridula Gupta, IEEE Trans. On Electron Devices, Vol. 62, No. 12, pp. 3965 – 3972, 2015. ISSN : 0018-9383
  79. Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-Molecules, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, Superlattices and Microstructures, Volume 88, December 2015, Pages 225-243. ISSN No. : 0749-6036, doi:10.1016/j.spmi.2015.09.013, Impact Factor: 2.097. 
  80. Nanoscale T-Shaped Double Gate DG MOSFET: Numerical Investigation for Analog/RF and Digital Performance, Vandana Kumari, Aravindan  Ilango, Manoj Saxena, Mridula Gupta, Superlattices and Microstructures, Volume 89, January 2016, Pages 97-111, ISSN 0749-6036, http://dx.doi.org/10.1016/j.spmi.2015.10.046.
  81. Linearity and Analog Performance Realization of Energy-Efficient TFET-Based Architectures: An Optimization for RFIC Design, Upasana, Rakhi Narang, Manoj Saxena, and Mridula Gupta, IETE Technical Review, VOL. 33, NO. 1, 23-28, 2016. ISSN 0377-2063 (Print), 0974-780X (Online) http://dx.doi.org/10.1080/02564602.2015.1043153 
  82. Investigation of Dielectric Pocket Induced Variations in Tunnel Field Effect Transistor, Upasana, Rakhi Narang, Manoj Saxena, and Mridula Gupta, Superlattices and Microstructures, Volume 92, April 2016, Pages 380–390.
  83. Impact of Interfacial Fixed Charges on the Electrical Characteristics of Pocket-Doped Double Gate Tunnel FET, Abhishek Mishra; Rakhi Narang, Manoj Saxena and Mridula Gupta, IEEE Transactions on Device and Materials Reliability, Volume 16, Issue 2, pp. 117 – 122, June 2016
  84. Drain Current Model for Hetero-Dielectric Based TFET Architectures: Accumulation to Inversion Mode Analysis, Upasana, Rakhi Narang, Manoj Saxena, Mridula Gupta, Journal of Nano Research Vol. 36, Volume 36, pp. 31-43, 2016. DOI: 10.4028/www.scientific.net/JNanoR.36.31 
  85. Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET, Vandana Kumari, Manoj Saxena, Mridula Gupta, Journal of Nano Research Vol. 36, Volume 36, pp. 51-63, 2016. Doi: 10.4028/www.scientific.net/JNanoR.36.51 
  86. NI Multisim and Experimental Validation Implementation of Ratioed Logic Gates Using Memristor, Rishav Kumar Pandey Arushi Gupta, Divya Goel, Poonam Kasturi, Mamta Amol Wagh, Manoj Saxena, Delhi University Journal of Undergraduate Research and Innovation (ISSN 2395 - 2334) Volume 2, Issue 1 pp 131-141, 2016.
  87. Simulation and Experimental Demonstration of Low-/High-Pass Filter using Memristors, Khushwant Sehra, Gaurav Kumar Shakya, Poonam Kasturi, Mamta Amol Wagh and Manoj Saxena, Delhi University Journal of Undergraduate Research and Innovation (ISSN 2395 - 2334) Volume 2, Issue 1 pp 98-108, 2016.
  88. pH sensing Characteristics of Silicon on Insulator (SOI) Junctionless (JL) ISFET , Ajay Singh, Rakhi Narang, Manoj Saxena, and Mridula Gupta, Advanced Science, Engineering and Medicine Volume 8, Number 12, December 2016, pp. 960-967(8) ISSN: 2164-6627 (print); EISSN: 2164-6635 (online)
  89. Numerical Analysis of Variability effects in Nanogap Embedded Dielectric Modulated Field Effect Transistor , Rakhi Narang, Manoj Saxena, and Mridula Gupta, Advanced Science, Engineering and Medicine, Volume 9, Number 2, February 2017, pp. 155-161(7)
  90. Underlapped FinFET on insulator: Quasi3D analytical model, Vandana Kumari, K. Sharmetha, Manoj Saxena, Mridula Gupta, Solid-State Electronics, Volume 129, March 2017, Pages 138–149
  91. Analytical Model of pH sensing Characteristics of Junctionless Silicon on Insulator ISFET, R. Narang, M. Saxena and M. Gupta, IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1742-1750, April 2017. doi: 10.1109/TED.2017.2668520 
  92. Drain Current Model for Double Gate (DG) p-n-i-n TFET: Accumulation to Inversion Region of Operation, Upasana, Rakhi Narang, Manoj Saxena, Mridula Gupta, Superlattices and Microstructures Volume 104, Pages 78–92, April 2017.
  93. Novel junctionless electrolyte-insulator-semiconductor field-effect transistor (JL EISFET) and its application as pH/biosensor, Ajay, Rakhi Narang, Manoj Saxena, Mridula Gupta, Microsystem and Technologies, Vol. 23 (8), pp. 3149-3159, August 2017. doi:10.1007/s00542-016-3013-1
  94. Modeling and Simulation Investigation of Sensitivity of Symmetric Split Gate Junctionless FET for Biosensing Application, Ajay; R. Narang; M. Saxena; M. Gupta, IEEE Sensors Journal, Vol. 17 (15), pp. 4853-4861, 2017. doi: 10.1109/JSEN.2017.2716102 
  95. Modeling of gate underlap junctionless double gate MOSFET as bio-sensor, R Narang, M Saxena, M Gupta, Materials Science in Semiconductor Processing 71, 240-251, November 2017. Doi: https://doi.org/10.1016/j.mssp.2017.08.008 
  96. Analytical Drain Current model for Gate and Channel Engineered RingFET (GCE-RingFET), Sachin Kumar, Vandana Kumari, Sanjeev Singh, Manoj Saxena and Mridula Gupta, Superlattices and Microstructures Vol. 111, pp. 1113-1120, 2017.
  97. Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-Effect Transistor as pH Sensor, Ajay Singh, Rakhi Narang, Manoj Saxena and Mridula Gupta, 21st  International Symposium on VLSI Design and Test  (VDAT 2017), 29th  June - 2nd  July 2017, IIT Roorkee, INDIA (organized by IIT Roorkee in association with IEEE UP Section and VLSI Society of India), Communications in Computer and Information Science, Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh (Eds.), pp. 249-258, ISBN 978-981-10-7470-7.
  98. Improved Gate Modulation in Tunnel Field Effect Transistors with non-rectangular tapered Y-Gate geometry, Rakhi Narang, Mridula Gupta and Manoj Saxena, 21st  International Symposium on VLSI Design and Test  (VDAT 2017), 29th  June - 2nd  July 2017, IIT Roorkee, INDIA (organized by IIT Roorkee in association with IEEE UP Section and VLSI Society of India), Communications in Computer and Information Science, Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh (Eds.), pp. 463-473, ISBN 978-981-10-7470-7.
  99. Variability Investigation of Double Gate JunctionLess (DG-JL) Transistor for Circuit Design Perspective, Vandana Kumari, Manoj Saxena and Mridula Gupta, 21st  International Symposium on VLSI Design and Test  (VDAT 2017), 29th  June - 2nd  July 2017, IIT Roorkee, INDIA (organized by IIT Roorkee in association with IEEE UP Section and VLSI Society of India), Communications in Computer and Information Science, Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh (Eds.), pp. 496-506, ISBN 978-981-10-7470-7.
  100. Reconnoiter the Leavening of Skin- Deep Insulated Extension On Analog Performance of RingFET, Sachin Kumar, Vandana Kumari, Sanjeev Singh, Manoj Saxena and Mridula Gupta, AEU-International Journal of Electronics and Communications 83, 67-72, January 2018
  101. Modeling and Simulation of Junctionless Double Gate Radiation Sensitive FET (RADFET) Dosimeter, Avashesh Dubey, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, IEEE Transactions on Nanotechnology, Volume: 17, Issue: 1, pp. 49-55, January 2018
  102. Empirical Model for Nonuniformly Doped Symmetric Double-Gate Junctionless Transistor, V Kumari, A Kumar, M Saxena, M Gupta, IEEE Transactions on Electron Devices, Vol. 65, No. 1, pp. 314-321, January 2018.
  103. Sub-threshold Drain Current model of Double Gate RingFET (DG-RingFET) Architecture: An Analog and Linearity Performance Investigation for RFIC Design, S Kumar, V Kumari, S Singh, M Saxena, M Gupta, IETE Technical Review 35 (2), 169-179, 2018
  104. Two-dimensional (2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET), Ajay Rakhi Narang, Manoj Saxena, Mridula Gupta, Journal of Computational Electronics, Volume 17, Issue 2, pp 713–723, June 2018
  105. Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) Transistor Including Source Drain Depletion Length: Model for Sub-threshold Behavior, Vandana Kumari, Ayush Kumar, Manoj Saxena, Mridula Gupta, Superlattices and Microstructures, Volume 113, Pages 57-70, January 2018,  https://doi.org/10.1016/j.spmi.2017.09.049
  106. Model of GaSb-InAs p-i-n Gate All Around BioTunnel FET, Ajay ; Rakhi Narang ; Manoj Saxena ; Mridula Gupta, IEEE Sensors Journal, Year: 2019 , Volume: 19 , Issue: 7, Pages: 2605 – 2612 DOI: 10.1109/JSEN.2018.2887277
  107. Exploring the applicability of well optimized dielectric pocket tunnel transistor for future low power applications, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, Superlattices and Microstructures, Volume 126, February 2019, Pages 8-16. https://doi.org/10.1016/j.spmi.2018.12.005 
  108. Comparative study of InGaN and InGaAs based dopingless TFET with different gate engineering techniques, 2019, Monika Sharma, Rakhi Narang, Manoj Saxena and Mridula Gupta, Advances in Natural Sciences: Nanoscience and Nanotechnology, Volume 10, Number 3, 035009, September 2019. https://doi.org/10.1088/2043-6254/ab38b1
  109. Investigation of total ionizing dose effect on SOI tunnel FET Avashesh Dubey, Rakhi Narang, Manoj Saxena, Mridula Gupta, Superlattices and Microstructures, Volume 133, 106186, September 2019 https://doi.org/10.1016/j.spmi.2019.106186 . 
  110. Improvement in DC and pulse characteristics of AlGaN/GaN HEMT by employing dual metal gate structure, Ajay Kumar Visvkarma Robert Laishram, Sonalee Kapoor, D S Rawal, Seema Vinayak and Manoj Saxena, Semiconductor Science and Technology, Volume 34, Number 10, 105013, October 2019
  111. Temperature based analysis of 3-step field plate AlGaN/GaN HEMT using numerical simulation, Neha, Vandana Kumari, Mridula Gupta and Manoj Saxena, Advances in Natural Sciences: Nanoscience and Nanotechnology, Volume 10, Number 4, 045006, December 2019. https://doi.org/10.1088/2043-6254/ab38b1
  112. Comparative study of Au and Ni/Au gated AlGaN/GaN high electron mobility transistors, Ajay Kumar Visvkarma, Chandan Sharma, Robert Laishram, Sonalee Kapoor,  D. S. Rawal, Seema Vinayak, and Manoj Saxena, AIP Advances 9, 125231 (2019); https://doi.org/10.1063/1.5116356

Research papers  published in Refereed/Peer Reviewed Conferences

Paper Published in International conferences: -

  1. Closed form Analytical Threshold Voltage Model of Dual Material Double-Gate (DUM-DG) MOSFET, Manoj Saxena, Subhasis Haldar, Mridula Gupta, and R. S. Gupta, 15th Asia Pacific Microwave Conference (APMC-2003), November 4-7, 2003, Seoul, Korea, pp. 1434-1437. (ISBN 9788988366110)
  2. Two-Dimensional analytical modeling and simulation of retrograde doped HMG-MOSFET, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, Proceedings. IEEE Lester Eastman Conference on High Performance Devices, 2004, August 4-6, 2004,Troy, New York, USA, pp. 52-59, 2004 (Print ISBN:981-256-196-X)
  3. Physics Based Modeling and Simulation of Epitaxial Channel Hetero Material Gate Stack (EPI-HEMGAS MOSFET), Kirti Goel, Manoj Saxena, Mridula Gupta and R. S. Gupta, 16th Asia Pacific microwave Conference, APMC, December 15th –18th, 2004, New Delhi, India, pp. 9-10. ISBN 8177647229
  4. Analytical Analysis and Simulation of High-K Dielectric in Gate Stack Silicon on Nothing (GAS-SON) MOSFET for Sub-100 nm Gate Length, Poonam Kasturi, Manoj Saxena, R.S. Gupta, 16th Asia Pacific Microwave Conference, APMC, December 15th –18th, 2004, New Delhi, India, pp. 65-67 ISBN 8177647229
  5. Two-Dimensional Analysis and Simulation for Gate Stack Silicon-On-Nothing MOSFET (GAS-SON MOSFET), Poonam Kasturi, Manoj Saxena, R.S. Gupta, 10th International Symposium on Microwave and Optical Technology, ISMOT 2005, Fukuoka, Japan, August 22–25, 2005, pp. 406-409 (ISBN 4990254619)
  6. Non-Uniformly Doped Gate Electrode Workfunction Engineered MOSFET: Novel Design Architecture for Controlling Short Channel Effect and Improving Gate Transport Efficiency, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, Thirteenth International Workshop on The Physics of Semiconductor Devices (IWPSD), New Delhi, India, December 13-17, 2005, pp. 995-1002. ISBN 8177649469, 9788177649468
  7. Investigating the role of Stacked Gate Oxide and Hetro-Material Gate on Electrical Characteristics of Insulated Shallow Extension (ISE) MOSFET Ravneet Kaur, Manoj Saxena and R. S. Gupta, Thirteenth International Workshop on The Physics of Semiconductor Devices (IWPSD), New Delhi, India, December 13-17, 2005 pp. 1163-1166. ISBN 8177649469, 9788177649468
  8. Physics based modeling and simulation of Hetero-Material Asymmetric Gate Stack Epi-MOSFET (HEMAGASE)-MOSFET, Kirti Goel, Manoj Saxena, Mridula Gupta, R. S. Gupta, 16th Asia Pacific Microwave Conference (APMC-2005), Suzhou, China, December 4-7, 2005, pp. 848-851. IEEE- Print ISBN:0-7803-9433-X
  9. Three Region Hetero-Material Gate Oxide Stack (TMGOS) Epi-MOSFET: A New Device Structure for Reduced Short Channel Effects, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, International Semiconductor Device Research Symposium (ISDRS), Bethesda, Bethesda, Maryland, USA, December 7-9, 2005, pp 72-73. IEEE- Print ISBN:1-4244-0083-X
  10. Comparison of Three Region Multiple Gate Nanoscale Structures for Reduced Short Channel Effects and High Device Reliability, Kirti Goel, Manoj Saxena and Mridula Gupta and R. S. Gupta, Workshop on Compact Modeling (WCM 06), Boston, Massachusetts, U.S.A., NSTI-Nanotech, pp. 816-819, May 9-11, 2006. ISBN 0976798565
  11. Gate Oxide Engineered Dual Material Gate Insulated Shallow Extension (GOXDMG-ISE) MOSFET: A New Vent to Wireless Communication, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, 3rd International Conference on Computers and Devices for Communication (CODEC-2006), Institute of Radio physics and Electronics, Calcutta, pp. 324-327, December 18-20, 2006
  12. Exploration of the Effect of Negative Junction Depth on the Electrical Characteristics of Concave DMG MOSFET in Sub-50-Nanometer Regime, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, 3rd International Conference on Computers and Devices for Communication (CODEC-2006), Institute of Radio physics and Electronics, Calcutta, pp. 317-319, December 18-20, 2006
  13. RF Performance Investigation of Gate Stacked Insulated Shallow Extension (ISE) MOSFET and Bulk: A Comparative Study, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Proceeding of Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 254-258. ISBN: 8184240260
  14. Design and FPGA realization of Direct Sequence-Spread Spectrum (DS-SS) BPSK Modulator using a Five Stage Gold Code Generator, Rishu Chaujar, Ravneet Kaur, Manoj Saxena and R. S. Gupta, Proceeding of Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 213-216. ISBN: 8184240260
  15. A TCAD study of sub-100 nm advance gate electrode workfunction engineered SON-MOSFET, R.S. Gupta, Manoj Saxena and Poonam Kasturi, 11th International Symposium on Microwave and Optical Technology (ISMOT-2007) , Villa Mondragone, Monte Porzio Catone, Italy on 17-21 December 2007, pp. 267-270. ISBN 9788854814769
  16. Scrutinize the Gate Misalignment Effects in Graded Channel DG FD SOI n-MOSFET, Rupendra Kumar Sharma, Manoj Saxena, Mridula Gupta and R.S. Gupta, 11th International Symposium on Microwave and Optical Technology (ISMOT-2007), Villa Mondragone, Monte Porzio Catone, Italy on 17-21 December 2007, pp, 821-824. ISBN 9788854814769
  17. Electrical Characterization of Insulated Shallow Extension (ISE) MOSFET: A Punchthrough Stopper, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, 11th International Symposium on Microwave and Optical Technology (ISMOT-2007), Villa Mondragone, Monte Porzio Catone, Italy on 17-21 December 2007, pp. 813-816. ISBN 9788854814769
  18. Pre-Distortion Linearity Enhancement for Sub-50nm Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, 11th International Symposium on Microwave and Optical Technology (ISMOT-2007), Villa Mondragone, Monte Porzio Catone, Italy on 17-21 December 2007, pp.797-800. ISBN 9788854814769
  19. Linearity assessment in DMG ISEGaS MOSFET for RFIC Design Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Nineteenth Asia Pacific Microwave Conference (APMC-2007), December 11-14, 2007, Bangkok, Thailand, pp.2495-2498. IEEE- E-ISBN : 978-1-4244-0749-1, Print ISBN: 978-1-4244-0748-4
  20. On-State and Switching Performance Investigation of Sub-50nm L-DUMGAC MOSFET Design for High-Speed Logic Applications, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Semiconductor Device Research Symposium (ISDRS), University of Maryland, USA, December 12-14, 2007, pp.1892-1893. IEEE- E-ISBN : 978-1-4244-1892-3, Print ISBN: 978-1-4244-1892-3
  21. A 2-D Analytical Subthreshold Model for Gate Misalignment Effects on Graded Channel DG FD SOI n-MOSFET, Rupendra Kumar Sharma, Manoj Saxena, Mridula Gupta and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) December 16-20, 2007, Mumbai, India, pp. 183-186. IEEE- E-ISBN : 978-1-4244-1728-5, Print ISBN: 978-1-4244-1728-5
  22. RF-Distortion in Sub-100nm L-DUMGAC MOSFET, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007). December 16-20, 2007, Mumbai, India, pp.168-170. 
  23. Two-Dimensional Analytical Threshold Voltage Model for Nanoscale SG-Concave MOSFET in Sub-50nm Regime, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007), December 16-20, 2007, Mumbai, India, pp. 221-224. 
  24. Nanoscale Insulated Shallow Extension MOSFET with Dual Material Gate for High Performance Analog Operations , Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) December 16-20, 2007, Mumbai, India, pp. 171-173. IEEE- E-ISBN : 978-1-4244-1728-5, Print ISBN: 978-1-4244-1728-5
  25. Subthreshold Performance Consideration of a Novel Architecture: ISEGaS deca-nanometer MOSFET, Ravneet Kaur, Rishu Chaujar, Manoj Saxena, and R. S. Gupta, Fourteenth International Workshop on the Physics of Semiconductor Devices (IWPSD-2007) December 16-20, 2007, Mumbai, India, pp.123-126. IEEE- E-ISBN : 978-1-4244-1728-5, Print ISBN: 978-1-4244-1728-5
  26. An Iterative Approach to Characterize Various Advanced Non-Uniformly Doped Channel Profile, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A. Nanotech 2008 Vol. 3, pp. 814-817. ISBN:9781420085075
  27. Pre-Distortion Assessment of Workfunction Engineered Multilayer Dielectric Design of DMG ISE SON MOSFET, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A. Nanotech 2008 Vol. 3, pp. 605-606. ISBN:9781420085075
  28. Assessment of L-DUMGAC MOSFET for High Performance RF Applications with Intrinsic Delay and Stability as Design Tools, R. Chaujar, R. Kaur, M. Saxena, M. Gupta and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A. Nanotech 2008 Vol. 3, pp. 586-589. ISBN:9781420085075
  29. Compact Analytical Threshold Voltage Model for Nanoscale Multi-Layered-Gate Electrode Workfunction Engineered Recessed Channel, R. Chaujar, R. Kaur, M. Saxena, M. Gupta and R. S. Gupta, 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A. Nanotech 2008 Vol. 3, pp. 873-876. ISBN:9781420085075
  30. Impact of Gate Stack Configuration onto the RF/analog Performance of ISE MOSFET, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, International Conference of Recent Advances in Microwave Theory and Applications, Microwave-2008 conference, Nov. 21 – 24, 2008 at Jaipur, pp. 686-688. IEEE- E-ISBN : 978-1-4244-2691-1, Print ISBN: 978-1-4244-2690-4
  31. GEWE-RC MOSFET: A solution to CMOS technology for RFIC design based on the concept of intercept point, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Conference of Recent Advances in Microwave Theory and Applications, Microwave-2008 conference, Nov. 21 – 24, 2008 at Jaipur, pp. 661-663. IEEE- E-ISBN : 978-1-4244-2691-1, Print ISBN: 978-1-4244-2690-4
  32. GEWE-RC MOSFET: High Performance RF Solution to CMOS Technology, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Asia Pacific Microwave Conference (APMC)-2008, December 16-19, 2008 in Hong Kong Convention and Exhibition Center, Hong Kong, China, art. no. 4958185. IEEE- E-ISBN : 978-1-4244-2642-3, Print ISBN: 978-1-4244-2641-6
  33. TCAD Performance Investigation of a Novel MOSFET Architecture of Dual Material Gate Insulated Shallow Extension Silicon on Nothing MOSFET for the ULSI-Era, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Asia Pacific Microwave Conference (APMC)-2008, December 16-19, 2008 in Hong Kong Convention and Exhibition Center, Hong Kong, China, art. no. 4958643. IEEE- E-ISBN : 978-1-4244-2642-3, Print ISBN: 978-1-4244-2641-6
  34. Impact of Multi-Layered Gate Design on Hot Carrier Reliability of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET, R. Chaujar, R. Kaur, M. Saxena, M. Gupta and R. S. Gupta, XXIX General Assembly of the International Union of Radio   Science (Union Radio Scientifique Internationale-URSI), Chicago, Illinois, USA on August 07-16, 2008. ISSN 00749516
  35. Solution to CMOS technology for high performance analog applications: GEWE-RC MOSFET , Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R. S. Gupta, 2nd  National Workshop on Advanced Optoelectronic Materials and Devices, AOMD 2008, art. no. 5075707, pp. 201-205, Print ISBN: 978-0-230-63718-4, INSPEC Accession Number: 10704394, 
  36. Analytical Drain Current Evaluation Technique for Various Non-Uniformly Doped MOS Device Architectures, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Symposium on Microwave and Optical Technology (ISMOT) – 2009, December 16-19,2009 in Hotel Ashok, New Delhi, India . ISBN 10:0230328466
  37. Evaluation of Multi-Layered Gate Design on GEWE-RC MOSFET for Wireless Applications in terms of Linearity-Distortion Issues, Rishu Chaujar, Manoj Saxena, Mridula Gupta and R.S. Gupta, International Symposium on Microwave and Optical Technology (ISMOT)-2009, December 16-19,2009 in Hotel Ashok, New Delhi, India. ISBN 10:0230328466
  38. Simulation Study of Stack Gate Insulated Shallow Extension Silicon On Nothing ISE-SON MOSFET for RFICs design, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, 2011 IEEE Students' Technology Symposium  at IIT Kharagpur during 14-16 January 2011, pp. 286-291. IEEE- Print ISBN:978-1-4244-8941-1
  39. Modeling and Simulation of multi layer gate dielectric Double Gate Tunnel Field-Effect Transistor (DG-TFET), Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, 2011 IEEE Students' Technology Symposium  at IIT Kharagpur during 14-16 January 2011. IEEE- Print ISBN:978-1-4244-8941-1
  40. Analysis and Simulation of Si/GaAs/GaN MESFET to study the impact of Localised charges on device performance, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, 2011 IEEE Students' Technology Symposium  at IIT Kharagpur during 14-16 January 2011, pp. 259-264. IEEE- Print ISBN:978-1-4244-8941-1
  41. Mixedmode Circuit Simulation of Silicon and Germanium Nanowire MOSFETs - A Comparative Study,Gaurav Mahahan, Rakhi Narang, Manoj Saxena and V. K. Chaubey, 2011 IEEE Students' Technology Symposium  at IIT Kharagpur during 14-16 January 2011, pp. 292-296. IEEE- Print ISBN:978-1-4244-8941-1
  42. Impact of Localized Charges on RF and Microwave Performance of Nanoscale Cylindrical Surrounding Gate MOSFET, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, 13thInternational Symposium on Microwave and Optical Technology, ISMOT 2011, Prague, Czech Republic, EU, June 20-23, 2011. ISBN9788001048870)
  43. RF Performance Analysis of Double Gate Tunneling Field Effect Transistor (DG-TFET), Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, 13th International Symposium on Microwave and Optical Tech. nology, ISMOT 2011, Prague, Czech Republic, EU, June 20-23, 2011. ISBN9788001048870)
  44. Comparative Study of Dielectric Pocket (DP) MOSFET Incorporating Buried Oxide Layer (BOX) with DP MOSFET for RF Applications, Vandana Kumai, Manoj Saxena, R. S. Gupta and Mridula Gupta,13th International Symposium on Microwave and Optical Technology, ISMOT 2011, Prague, Czech Republic, EU, June 20-23, 2011. ISBN9788001048870
  45. Asymmetric Gate Oxide Tunnel Field Effect Transistor for Improved Performance , Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference On Devices Circuits and Systemes (ICDCS’12)  during March 15 - 16, 2012, Karunya Institute of Technology & Sciences, Coimbatore, India, pp. 284-287, 2012. IEEE- Print ISBN: 978-1-4577-1545-7
  46. Laterally Asymmeterc Channel Insulated Shallow Extension (LAC-ISE-SON) MOSFET for improved reliability and digital circuit simulation, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference On Devices Circuits and Systemes (ICDCS’12)  during March 15 - 16, 2012, Karunya Institute of Technology & Sciences, Coimbatore, India, pp. 288-292, 2012. IEEE- Print ISBN: 978-1-4577-1545-7
  47. Impact of the localized Charges in the iNterficial Layer of the Schottky Contact in SOI MESFET, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta,  International Conference On Devices Circuits and Systemes (ICDCS’12)  during March 15 - 16, 2012, Karunya Institute of Technology & Sciences, Coimbatore, India, pp. 312-315, 2012.  IEEE- Print ISBN: 978-1-4577-1545-7
  48. Analytical Drain Current Model for Damaged Gate All Around (GAA) MOSFET Including Quantum and Velocity Overshoot Effects, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, NSTI-Nanotech 2012 Conference and Expo, June 18-21, 2012, Santa Clara, USA, Vol. 2, pp.716-719, 2012. http://www.techconnectworld.com/World2012/a.php?i=1557. ISBN:9781466562875
  49. Physics based Analytical Model for a Pocket Doped p-n-p-n Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, NSTI-Nanotech 2012 Conference and Expo, June 18-21, 2012, Santa Clara, USA, Vol. 2, pp.776-779, 2012. http://www.techconnectworld.com/World2012/a.php?i=1555 . ISBN:9781466562875
  50. Analytical Model for a Dielectric Modulated Double Gate FET (DM-DG-FET) Biosensor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Emerging Electronics, Jointly organized by IIT Bombay & IISc Bangalore  during December 15-17, 2012. IEEE- Print ISBN: 978-1-4673-3135-7
  51. Temperature Dependent Model for Dielectric Pocket Double Gate (DPDG) MOSFET: A Novel Device Architecture, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta,  International Conference on Emerging Electronics, Jointly organized by IIT Bombay & IISc Bangalore  during December 15-17, 2012. IEEE- Print ISBN: 978-1-4673-3135-7
  52. Theoretical investigation of back gate bias effect on the electrostatic integrity of Insulated Shallow Extension Silicon on Void (ISESOV) MOSFET, Vandana Kumari, Mridula  Gupta, Neha Bhushan, Manoj Saxena and R.S. Gupta, 2012 Annual IEEE India Conference, INDICON 2012 , art. no. 6420706 , pp. 694 – 699, 2012. IEEE-Print ISBN:978-1-4673-2270-6.
  53. Surface Potential based Analytical Model for Hetero-Dielectric p-n-i-n Double-Gate Tunnel-FET, Upasana, Rakhi Narang, Manoj Saxena, and Mridula Gupta, IWPSD 2013, Amity University, 10-13 December 2013 (Accepted for Poster Presentation) IWPSD 2013, Physics of Semiconductor Devices, Environmental Science and Engineering, Springer International Publishing, pp 171-174, 2014. Available Online: 10.1007/978-3-319-03002-9_75. (Print ISBN: 978-3-319-03001-2, Online ISBN: 978-3-319-03002-9, Series ISSN: 1863-5520)
  54. Ambipolar behaviour of Tunnel Field Effect Transistir (TFET) as an advantage for Biosensiing Applications, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, IWPSD 2013, Amity University, 10-13 December 2013 (Accepted for Poster Presentation) IWPSD 2013, Physics of Semiconductor Devices, Environmental Science and Engineering, Springer International Publishing, pp 295-298, 2014. Available Online: 10.1007/978-3-319-03002-9_75. (Print ISBN: 978-3-319-03001-2, Online ISBN: 978-3-319-03002-9, Series ISSN: 1863-5520)
  55. Simulation Study for Dual Material Gate Hetero- Dielectric TFET: Static Performance Analysis for Analog Applications, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, INDICON 2013, December 13-15, 2013, Victor Menezes Convention Centre (VMCC), IIT Bombay, Mumbai, INSPEC Accession Number:14062367, 2013. IEEE- Print ISBN:978-1-4799-2274-1
  56. Investigation of Dielectric-Modulated Double-Gate Junctionless MOSFET For Detection of Biomolecules, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, INDICON 2013, December 13-15, 2013, Victor Menezes Convention Centre (VMCC), IIT Bombay, Mumbai, INSPEC Accession Number:14062368, 2013. IEEE- Print ISBN:978-1-4799-2274-1
  57. “Hot Carrier Reliability and linearity Performance Investigation of Nanoscale RinFET for RFIC Design” Sachin Kumar, Vandana Kumari, Manoj Saxena, Mridula Gupta, International Conference on Microwave, Antenna, Propagation and Remote sensing (ICMARS 2013), 11th – 14th December pp.40-44. (Best Student Paper Award)
  58. Switching Performance analyses of Gate Material and Gate Dielectric Engineered TFET Architectures and Impact of Interface Oxide Charges, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, International Conference on Devices, Circuits and Systems – ICDCS 2014. ICDCS 2014 held during Mar 6-8, 2014 in Karunya University, Coimbatore, Tamil Nadu, India, INSPEC Accession Number: 14685215, IEEE- http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6926182 
  59. Analytical Modeling of a Split-Gate Dielectric Modulated Metal-Oxide-Semiconductor Field-Effect Transistor for Application as a Biosensor, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, International Conference on Devices, Circuits and Systems – ICDCS 2014. ICDCS 2014 held during Mar 6-8, 2014 in Karunya University, Coimbatore, Tamil Nadu, India, INSPEC Accession Number: 14685228, http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6926183 
  60. TCAD Assesment of Dual Material Gate Nanoscale RingFET (DMG-RingFET) for Analog and Digital Applications, Sachin Kumar, Vandana Kumari, Manoj Saxena, Mridula Gupta, International Conference on Devices, Circuits and Systems – ICDCS 2014. ICDCS 2014 held during Mar 6-8, 2014 in Karunya University, Coimbatore, Tamil Nadu, India, INSPEC Accession Number: 14685183, IEEE- http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6926181 
  61. Charge Based Modeling of Channel Material Engineered P-type Double Gate MOSFET, Vandana Kumari, Aravindan llango, Manoj Saxena, Mridula Gupta, International Conference on Emerging Electronics (ICEE) held at J N Tata Auditorium, Indian Institute of Science during December 4-6, 2014, IEEE-Print ISBN: 978-1-4673-6527-7, INSPEC Accession Number: 15290580. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7151141 
  62. Impact of dry and watery environment on the sensitivity of split gate metal oxide field effect transistor for biosensing application, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, Published in Proceedings of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 1-4 June 2015, pp. 729 – 732, Print ISBN: 978-1-4799-8362-9, INSPEC Accession Number: 15506170, Conference Location : Singapore, http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7285220 , Publisher: IEEE
  63. Influence of dielectric pocket on electrical characteristics of tunnel field effect transistor: A study to optimize the device efficiency, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, Published in Proceedings of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 1-4 June 2015, pp. 762 – 765, Print ISBN: 978-1-4799-8362-9, INSPEC Accession Number: 15506244, Conference Location : Singapore, http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7285229 , Publisher: IEEE.
  64. Polarity and ambipolarity controllable (PAC) tunnel field effect transistor, Rakhi Narang, Manoj Saxena and Mridula Gupta , Published in Proceedings of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 1-4 June 2015, pp. 333-336, Print ISBN: 978-1-4799-8362-9, INSPEC Accession Number: 15506117, Conference Location : Singapore, http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7285118 , Publisher: IEEE.
  65. Analysis of Gate Underlap Channel Junctionless Double Gate MOSFET as a Sensor, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta presented in 6th International Conference on Computers and Devices for Communication (CODEC-15) ((To appear in IEEE Explore)
  66. Modeling and Simulation Study of Gate Material Engineered TFET Architecture Considering the Impact of Mobile Charge Carriers, Understanding Device Physics in Different Operational Regimes, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, 6th International Conference on Computers and Devices for Communication (CODEC-15), Electronic ISBN: 978-1-4673-9513-7; CD-ROM ISBN: 978-1-4673-9511-3; Print on Demand(PoD) ISBN: 978-1-4673-9514-4; INSPEC Accession Number: 16792367; DOI: 10.1109/CODEC.2015.7893196
  67. Analysis of Cylindrical Gate Junctionless Tunnel Field Effect Transistor (CG-JL-TFET), Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, Published in: 2015 Annual IEEE India Conference (INDICON), Date of Conference: 17-20 Dec. 2015, Page(s): 1 – 5, Print ISBN:978-1-4673-7398-2, INSPEC Accession Number: 15888327, Conference Location : New Delhi, DOI: 10.1109/INDICON.2015.7443557; Publisher: IEEE
  68. Merits of designing  Tunnel Field Effect Transistors with Underlap near Drain region, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, Published in: 2015 Annual IEEE India Conference (INDICON), Date of Conference: 17-20 Dec. 2015, Page(s): 1 - 5; Print ISBN: 978-1-4673-7398-2, INSPEC Accession Number: 15888323, Conference Location : New Delhi, DOI: 10.1109/INDICON.2015.7443560, Publisher: IEEE
  69. Investigation of III-V Compound Semiconductor Materials on Analog performance of Nanoscale RingFET, Sachin Kumar, Vandana Kumari, Manoj Saxena, Mridula Gupta, Published in: 2015 Annual IEEE India Conference (INDICON), Date of Conference: 17-20 Dec. 2015, Page(s): 1 – 5, Print ISBN: 978-1-4673-7398-2, INSPEC Accession Number: 15888438, Conference Location : New Delhi, DOI:10.1109/INDICON.2015.7443776, Publisher: IEEE
  70. "Analysis of GaSb-InAs Gate all around (GAA) p-i-n tunnel FET (TFET) for application as a bio-sensor,", Ajay, M. Gupta, R. Narang and M. Saxena, 2016 IEEE International Nanoelectronics Conference (INEC), Chengdu, China, 2016, pp. 1-2. doi: 10.1109/INEC.2016.7589324 Electronic ISBN: 978-1-4673-8969-3, Print on Demand(PoD) ISBN: 978-1-4673-8970-9; Electronic ISSN: 2159-3531
  71. "Analytical model of junctionless double gate radiation sensitive FET (RADFET) dosimeter,", A. Dubey, Ajay, M. Gupta, R. Narang and M. Saxena, 2016 IEEE International Nanoelectronics Conference (INEC), Chengdu, China, 2016, pp. 1-2; doi: 10.1109/INEC.2016.7589328. Electronic ISBN: 978-1-4673-8969-3, Print on Demand(PoD) ISBN: 978-1-4673-8970-9; Electronic ISSN: 2159-3531
  72. V. Kumari, M. Saxena and M. Gupta, "Sub-threshold drain current modeling of tri-gate dielectric pocket InGaAs-On-Nothing MOSFET," 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, 2016, pp. 193-198; doi: 10.1109/ICDCSyst.2016.7570592. Electronic ISBN: 978-1-5090-2309-7, Print on Demand(PoD) ISBN: 978-1-5090-2310-3
  73. Ajay, R. Narang, M. Saxena and M. Gupta, "Analytical model of gate underlap Double Gate Junctionless MOSFET as a bio-sensor," 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), Coimbatore, 2016, pp. 152-156; doi: 10.1109/ICDCSyst.2016.7570649. Electronic ISBN: 978-1-5090-2309-7, Print on Demand(PoD) ISBN: 978-1-5090-2310-3 (Presented)
  74. A. Dubey, Ajay, M. Gupta, R. Narang and M. Saxena, "Analytical model of junctionless double gate radiation sensitive FET (RADFET) dosimeter," 2016 IEEE International Nanoelectronics Conference (INEC), May 9-11,2016, Chengdu, China, pp. 1-2. doi: 10.1109/INEC.2016.7589328 Electronic ISSN: 2159-3531, ISBN:978-1-4673-8969-3, IEEE Catalog Number:CFP16625 
  75. Ajay, M. Gupta, R. Narang and M. Saxena, "Analysis of GaSb-InAs Gate all around (GAA) p-i-n tunnel FET (TFET) for application as a bio-sensor," 2016 IEEE International Nanoelectronics Conference (INEC), May 9-11,2016, Chengdu, China, pp. 1-2. doi: 10.1109/INEC.2016.7589324 Electronic ISSN: 2159-3531, ISBN:978-1-4673-8969-3, IEEE Catalog Number:CFP16625
  76. NI MULTISIM Implementation of Memristor Based Secured Communication System, Khushwant Sehra Poonam Kasturi Mamta Amol Wagh and Manoj Saxena, Proceedings of National Conference on Advancements in Electronics and Computer Applications NCAECA 2016 (UGC and DiETY Sponsored) held during Feb 04-05, 2016 at Shaheed Rajguru College of Applied Sciences, University of Delhi. Pp. 19-24, ISBN 978-93-5254-496-7 published by M/s Paramount Publishing House 
  77. Analytical Modeling and Simulation Study of Homo and Hetero III-V Semiconductor Based Tunnel Field Effect Transistor (TFET), M. Lakshmi Varshika, Rakhi Narang, Mridula Gupta and Manoj Saxena, In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 1185-1194, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_181
  78. Study of Extended Back Gate Double Gate JunctionLess Transistor: Theoretical and Numerical Investigation, Vandana Kumari, Abhineet Sharan, Manoj Saxena and Mridula Gupta In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 633-642, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_98
  79. Analytical Model for Tapered Gate Electrode Double Gate MOSFET Incorporating Fringing Field Effects, Rakhi Narang, Gokulnath Rajendran, Mridula Gupta and Manoj Saxena, In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 697-705, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_108
  80. Investigation of Sensitivity of Gate Underlap Junctionless DG MOSFET for Biomolecules, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 717-724, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_110
  81. Floating Gate Junction-Less Double Gate Radiation Sensitive Field Effect Transistor (RADFET) Dosimeter: A Simulation Study, Avashesh Dubey, Rakhi Narang, Manoj Saxena and Mridula Gupta In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 571-576, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_89
  82. Optically Controlled Silicon on Nothing MOSFET-Numerical Simulation, Vandana Kumari, Manoj Saxena and Mridula Gupta, In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 1071-1076, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI:https://doi.org/10.1007/978-3-319-97604-4_164
  83. Simulation Study on Stability Aspect of Dual Metal Dual Dielectric Based TFET Architectures Against Temperature Variations, Upasana, Rakhi Narang, Manoj Saxena and M. Gupta, In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 649-655, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_100
  84. Optimization of Gate Oxide of Dual-Gate MISHEMTs for Enhanced DC performance, Preeti Singh ; Vandana Kumari ; Manoj Saxena ; Mridula Gupta, 4th  IEEE International Conference on Devices, Circuits and Systems (ICDCS’18), Karunya University, Coimbatore, India, 16-17 March 2018, Page(s):121 – 125, IEEE Explore (oral presentation), https://ieeexplore.ieee.org/document/8605124 
  85. TCAD Based Investigation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) Transistor, Vandana Kumari, Manoj Saxena and Mridula Gupta, International Conference on Microelectronics Devices and Technology MicDAT-2018, Barcelona, Spain, June 20-22 2018.
  86. Threshold Voltage Investigation of Recessed Dual-Gate MISHEMT: Simulation Study, (paper ID- 151), P Singh, V Kumari, M Saxena and M Gupta, 22nd International Symposium on VLSI Design and Test (VDAT2018), Thiagarajar College of Engineering, Madurai, Tamilnadu, India, 28th June- 30th June 2018 (oral presentation).
  87. Simulation Based Breakdown Voltage Analysis of 3-Step Field AlGaN/GaN HEMTs, Neha, Vandana Kumari, Mridula Gupta, Manoj Saxena, 4th IEEE International Conference on Devices, Circuits and Systems (ICDCS’18), Karunya University, Coimbatore, India, Jan 2018 (oral presentation), ISBN 2018978-1-5386-3476-9/18, pp. 169-
  88. Comparative study of CMOS based dosimeter for gamma radiation, Avashesh Dubey, Rakhi Narang, Manoj Saxena and Mridula Gupta, 4th  IEEE International Conference on Devices, Circuits and Systems (ICDCS’18), Karunya University, Coimbatore, India, 16-17 March 2018, Page(s):117 – 120, IEEE Explore (oral presentation), https://ieeexplore.ieee.org/document/8605158 
  89. Investigation of Gate All Around Junctionless Nanowire Transistor with Arbitrary Polygonal Cross Section, Monika Sharma ; Mridula Gupta ; Rakhi Narang ; Manoj Saxena, 4th  IEEE International Conference on Devices, Circuits and Systems (ICDCS’18), Karunya University, Coimbatore, India, 16-17 March 2018, Page(s):159 – 163, IEEE Explore (oral presentation) https://ieeexplore.ieee.org/document/8605133 
  90. Evaluation of Dual-Gate MISHEMT with Sapphire, SiC and Silicon substrate, Preeti Singh, Vandana Kumari, Manoj Saxena and Mridula Gupta, 4th edition of the International Conference ‘NANOCON 018’ is being organized in collaboration with North Carolina A & T, State University Greensboro, USA, Joint School of Nanoscience and Nanoengineering (JSNN), Greensboro, USA, Tuskegee University, USA and Drexel University, USA. during 25-26 October 2018 at Bharati Vidyapeeth University, Pune-Satara Road Campus, Pune. 
  91. Temperature Based Analysis of 3-Step Field Plate AlGaN/GaN HEMT using Numerical Simulation, Neha, Vandana Kumari, Mridula Gupta and Manoj Saxena, 4th edition of the International Conference ‘NANOCON 018’ is being organized in collaboration with North Carolina A & T, State University Greensboro, USA, Joint School of Nanoscience and Nanoengineering (JSNN), Greensboro, USA, Tuskegee University, USA and Drexel University, USA. during 25-26 October 2018 at Bharati Vidyapeeth University, Pune-Satara Road Campus, Pune. 
  92. Comparative study of InGaN and InGaAs Dopingless TFET with different Gate Engineering Techniques, Monika Sharma, Rakhi Narang, Manoj Saxena, Mridula Gupta, 4th edition of the International Conference ‘NANOCON 018’ is being organized in collaboration with North Carolina A & T, State University Greensboro, USA, Joint School of Nanoscience and Nanoengineering (JSNN), Greensboro, USA, Tuskegee University, USA and Drexel University, USA. during 25-26 October 2018 at Bharati Vidyapeeth University, Pune-Satara Road Campus, Pune. 
  93. Investigation of Field Plate Misalignment on Electrical Characteristics of AlGaN/ GaN HEMT, Khushwant Sehra, Vandana Kumari, Mridula Gupta, Manoj Saxena, 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), 2-4 Nov 2018 Jointly Organised By Madan Mohan Malaviya University of Technology, Gorakhpur (U.P) INDIA & University of the Ryukyus, Okinawa, Japan (IEEE Conference Record Number:43684)
  94. Ajay Kumar Visvkarma, Robert Laishram, Chandan Sharma, Niraj Kumar, D S Rawal and Manoj Saxena. “Effect of Nitrogen Plasma on AlGaN/GaN HEMT Devices” 4th edition of the International Conference ‘NANOCON 018’ is being organized in collaboration with North Carolina A & T, State University Greensboro, USA, Joint School of Nanoscience and Nanoengineering (JSNN), Greensboro, USA, Tuskegee University, USA and Drexel University, USA. during 25-26 October 2018 at Bharati Vidyapeeth University, Pune-Satara Road Campus, Pune.
  95. Ajay Kumar Visvkarma, Robert Laishram, Chandan Sharma, Niraj Kumar, D S Rawal and Manoj Saxena, “Study of TiN/Au Schottky Contacts on AlGaN/GaN HEMT Fabricated by Reactive Sputtering”, International Workshop on Nano/Micro 2D-3D Fabrication, Manufacturing of Electronic-Biomedical Devices & Applications (IWNEBD)-2018 held from 31st Oct 2018 to 02nd Nov 2018 at IIT Mandi, Himachal Pradesh, India.
  96. RingFET Architecture for High Frequency Applications: TCAD based Assessment, Vandana Kumari, Manoj Saxena and Mridula Gupta, 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), The Pride Hotel, Kolkata, India during November 24-25, 2018. Organized by IEEE EDS Kolkata Chapter
  97. Sub-threshold Drain Current Model of Shell-Core Architecture Double Gate JunctionLess Transistor, Vandana Kumari, Ayush Kumar, Manoj Saxena and Mridula Gupta, 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), The Pride Hotel, Kolkata, India during November 24-25, 2018. Organized by IEEE EDS Kolkata Chapter
  98. Studying the Impact of Compound Semiconductor Material in Drain Region Extended Tunnel Transistor for SoC Applications, Upasana, Hasti Kasundra, Mridula Gupta and Manoj Saxena, 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), The Pride Hotel, Kolkata, India during November 24-25, 2018. Organized by IEEE EDS Kolkata Chapter
  99. Breakdown Voltage Analysis of Different Field Plate AlGaN/GaN HEMTs : TCAD Based Assesment, Neha Dahiya, Vandana Kumari, Mridula Gupta, Manoj Saxena, 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON), The Pride Hotel, Kolkata, India during November 24-25, 2018. Organized by IEEE EDS Kolkata Chapter
  100. K. Sehra, V. Kumari, V. Nath, M. Gupta and M. Saxena, 2019, Optimization of Asymmetric π Gate HEMT for Improved Reliability & Frequency Applications, 2019 IEEE 9th International Nanoelectronics Conferences (INEC), Kuching, Malaysia, 2019, pp.1-4. doi: 10.1109/INEC.2019.8853857
  101. K. Sehra, V. Kumari, V. Nath, M. Gupta, D. S. Rawal and M. Saxena, 2019, Comparison of Linearity and Intermodulation Distortion Metrics for T - and Pi - Gate HEMT," 2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON), ALIGARH, India, 2019, pp. 1-6. doi: 10.1109/UPCON47278.2019.8980221
  102. M. Lakshmi Varshika, Rakhi Narang, Mridula Gupta and Manoj Saxena, 2019, Analytical Modeling and Simulation Study of Homo and Hetero III-V Semiconductor Based Tunnel Field Effect Transistor (TFET), In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 1185-1194, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_181
  103. Vandana Kumari, Abhineet Sharan, Manoj Saxena and Mridula Gupta, 2019, Study of Extended Back Gate Double Gate JunctionLess Transistor: Theoretical and Numerical Investigation, In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 633-642, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_98
  104. Rakhi Narang, Gokulnath Rajendran, Mridula Gupta and Manoj Saxena, 2019, Analytical Model for Tapered Gate Electrode Double Gate MOSFET Incorporating Fringing Field Effects, In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 697-705, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_108
  105. Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, 2019, Investigation of Sensitivity of Gate Underlap Junctionless DG MOSFET for Biomolecules, In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 717-724, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_110
  106. Avashesh Dubey, Rakhi Narang, Manoj Saxena and Mridula Gupta, 2019, Floating Gate Junction-Less Double Gate Radiation Sensitive Field Effect Transistor (RADFET) Dosimeter: A Simulation Study, In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 571-576, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_89
  107. Vandana Kumari, Manoj Saxena and Mridula Gupta, 2019, Optically Controlled Silicon on Nothing MOSFET-Numerical Simulation, In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 1071-1076, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI:https://doi.org/10.1007/978-3-319-97604-4_164
  108. Upasana, Rakhi Narang, Manoj Saxena and M. Gupta, 2019, Simulation Study on Stability Aspect of Dual Metal Dual Dielectric Based TFET Architectures Against Temperature Variations, In: Sharma R., Rawal D. (eds) The Physics of Semiconductor Devices. IWPSD 2017. Springer Proceedings in Physics, vol 215.  pp 649-655, Print ISBN 978-3-319-97603-7, Online ISBN 978-3-319-97604-4, DOI: https://doi.org/10.1007/978-3-319-97604-4_100
     

Abstracts in International Conferences

  1. HEMGAS: A Novel Gate Workfunction Engineered Stacked Gate Oxide Concept for Sub-50 nm DG-MOSFET, Manoj Saxena, Subhasis Haldar, Mridula Gupta, and R. S. Gupta, 2nd International conference on Computer and Devices for communications, CODEC-2004, January 1-3, 2004 in Calcutta, India, pp. 155
  2. Dual-Material Gate Asymmetric Oxide (DMGASYMOX) Stack MOSFET: A Novel Device Architecture for Improved Carrier Transport Efficiency and Reduced Hot Electron Effects, Kirti Goel, Manoj Saxena, Mridula Gupta, R. S. Gupta International Union of Radio Science (URSI), New Delhi, India, October 23-29, 2005.
  3. Dual Material Gate (DMG) SOI-MOSFET with Dielectric Pockets: Innovative Sub-50 nm design for improved switching performance, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007) December 19 –21, 2007, Department of Physics & Astrophysics, University of Delhi, Delhi, pp. 109
  4. Two-Dimensional Analytical Modeling and Simulation of Rectangular Gate Recessed Channel (RG-RC) Nanoscale MOSFET in Sub-50nm Regime, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Indo-Australian Symposium on Multifunctional Nanomaterials, Nanostructures and Applications (MNNA 2007) December 19 –21, 2007, Department of Physics & Astrophysics, University of Delhi, Delhi, pp. 110.
  5. TCAD investigation of a Novel MOSFET architecure of DMG ISE SON MOSFETs for ULSI era, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 18-19
  6. Analytical analysis of subthreshold performance of sub-100 nm advanced MOSFET structures – An iterative approach, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 20-21
  7. Modeling and 2-D simulation of Nanoscale SON MOSFET, Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 22-24
  8. Performance advantage of air as buried dielectric in sub-100 nm silicon-on-nothing (SON) MOSFET with gate stack architecture, Poonam Kasturi, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 25-26
  9. Sub-threshold drain current performance assessment of MLGEWE-RC MOSFET for CMOS technology, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 27-28
  10. RF performance assessment of L-DUMGAC MOSFET for furure CMOS technology in gigahertz regime, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta, Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program, pp. 29-30
  11. A Unified Two Dimensional Analytical Model of  optically Controlled Silicon On  Insulator  MESFET ( OPSOI ) for advanced channel materials, Rajni Gautam, Manoj Saxena, R.S. Gupta and Mridula Gupta, The International Conference on Fiber Optics and Photonics – PHOTONICS, December 11-15,2010, IIT Guwahati 
  12. A 2-D Subthreshold Analytical model for Short Channel Effects in Nanowire MOSFETs (Si, Ge), Gaurav Mahajan, Rakhi Narang, Manoj Saxena, V.K. Chaubey, Nirma University International Conference on Engineering (NUiCONE) 2010, December 09-11, 2010, Nirma University, Ahmedabad
  13. Fabrication and Time degradation study of mercuric iodide (Red) single crystal X-Ray detector, Kulvinder Singh and Manoj Saxena, International Symposium on Semiconductor Materials and Devices (ISSMD), M. S. University Vadodara, Gujarat, January 28-30, 2011 
  14. Immunity Against Temperature Variability and Bias Point Invariability in Double Gate Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Materials for Advance Technologies, (ICMAT 2011), June 26, 2011 – July 01, 2011, Singapore(ABSTRACT appeared in Proceedings)
  15. SiGe Metal Semiconductor Field Effect Transistor (MESFET) Photodectetor Having Tailorable Photoresponse Using Bandgap Engineering, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Materials for Advance Technologies, (ICMAT 2011), June 26, 2011 – July 01, 2011, Singapore (ABSTRACT appeared in Proceedings)
  16. Simulation Study of Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for High Temperature Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Materials for Advance Technologies, (ICMAT 2011), June 26, 2011 – July 01, 2011, Singapore(ABSTRACT appeared in Proceedings)
  17. Nanoscale Double Gate Silicon On Nothing (DGSON) MOSFET: Promising Device Design for Wide Range of Operating Temperatures, Vandana Kumari, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Conference on Latest Trends in Nanoscience and Nanotechnology (ICNSNT), 28th -29th  March 2011, Karnataka, India
  18. Impact of a low bandgap material on the Linearity of a DG-TFET: A Comparative Study, Rakhi Narang, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Conference on Latest Trends in Nanoscience and Nanotechnology (ICNSNT), 28th -29th  March 2011, Karnataka, India
  19. Study of Performance Degradation of the Nanoscale Cylindrical Surrounding Gate MOSFET due to Hot Carrier Induced Localized Charges, Rajni Gautam, Manoj Saxena, Mridula Gupta and R. S. Gupta, International Conference on Latest Trends in Nanoscience and Nanotechnology (ICNSNT), 28th -29th  March 2011, Karnataka, India
  20. High Sensitivity Photodetector Using Si/Ge/GaAs Metal Semiconductor Field Effect Transistor (MESFET), Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, OPTICS 2011, May 23-25, 2011, Calicut, Kerala, India 
  21. Effect of Temperature and Gate Stack on the Linearity and Analog Performance of Double Gate Tunnel FET, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, The Second International Workshop on VLSI (VLSI 2011) in conjunction with (NECOM-2011), Venue: The Park Hotels, July 15 ~ 17, 2011, Chennai, India. 
  22. Channel Material Engineered Nanoscale Cylindrical Surrounding Gate MOSFET With Interface Fixed Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, The Second International Workshop on VLSI (VLSI 2011) in conjunction with (NECOM-2011), Venue: The Park Hotels, July 15 ~ 17, 2011, Chennai, India.
  23. Drain Current Model of Nanoscale Dual Material Gate (DMG) MOSFET including interfacial hot-carrier-induced degradation effect", Mini, Vandana Kumai, Manoj Saxena, R. S. Gupta and Mridula Gupta, International Conference on Microwaves, Antenna, Propagation and Remote Sensing, ICMARS-2011, Jaipur, India
  24. Influence of Localised charges on the temperature sensitivity of Si nanowire MOSFET, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, XVI International Workshop on the Physics of Semiconductor Devices, IWPSD 2011, December 19-22, 2011, IIT Kanpur
  25. Temperature Dependent RF/microwave Characteristics of Nanowire Surrounding Gate MOSFET with Localised Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta,  International Conference on Nanoscience and Technology (ICONSAT – 2012), January 20 to 23, 2012 at Hyderabad, India.
  26. Dynamic Performance Comparison of p-i-n and p-n-p-n Tunnel Field Effect Transistor and Impact of Gate Drain underlap , Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta,  International Conference on Nanoscience and Technology (ICONSAT – 2012), January 20 to 23, 2012 at Hyderabad, India.
  27. Nano-scale Empty Space in Double Gate (ESDG) MOSFET for High Performance Digital Applications: A Theoretical Study, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta,  International Conference on Nanoscience and Technology (ICONSAT – 2012), January 20 to 23, 2012 at Hyderabad, India. 
  28. Impact of temperature variations on the device and circuit performance of Tunnel FET - A Simulation Study, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, NANOCON 2012 – Second International Conference on Nanotechnology - Innovative Materials, Processes, Products and Applications  during October 18-19 2012, at Bharati Vidyapeeth University, Pune, India, pp.99 
  29. Comparative Study of Silicon On Nothing and III-V On Nothing Architecture for High Speed and Low Power Analog and RF/Digital Applications, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, NANOCON 2012 – Second International Conference on Nanotechnology - Innovative Materials, Processes, Products and Applications  during October 18-19 2012, at Bharati Vidyapeeth University, Pune, India, pp.105 
  30. Gate All Around MOSFET with Catalytic Metal Gate for Gas Sensinga Applications, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, NANOCON 2012 – Second International Conference on Nanotechnology - Innovative Materials, Processes, Products and Applications  during October 18-19 2012, at Bharati Vidyapeeth University, Pune, India, pp.106 
  31. Drain Current Model for Hetero-Dielectric based TFET Architectures: Accumulation to Inversion Mode Analysis , Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, NANOCON 2014 – Third International Conference on Nanotechnology during October 14-15, 2014 organized by Bharati Vidyapeeth University, Pune, India at  Le-Meridien Hotel, Pune  
  32. Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET, Vandana Kumari, Manoj Saxena, Mridula Gupta, NANOCON 2014 – Third International Conference on Nanotechnology during October 14-15, 2014 organized by Bharati Vidyapeeth University, Pune, India at  Le-Meridien Hotel, Pune 
  33. pH sensing Characteristics of Silicon on Insulator (SOI) Junctionless (JL) ISFET, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, NANOCON 2014 – Third International Conference on Nanotechnology during October 14-15, 2014 organized by Bharati Vidyapeeth University, Pune, India at  Le-Meridien Hotel, Pune 
  34. TCAD Assessment of Nanoscale Double Gate RingFET (DG-RingFET) Architecture: Analog and Linearity Performance Investigation for RFIC Design , Sachin Kumar, Vandana Kumari, Manoj Saxena, Mridula Gupta, NANOCON 2014 – Third International Conference on Nanotechnology during October 14-15, 2014 organized by Bharati Vidyapeeth University, Pune, India at  Le-Meridien Hotel, Pune 
  35. Numerical Analysis of Variability effects in Nanogap Embedded Dielectric Modulated Field Effect Transistor, Rakhi Narang, Manoj Saxena and Mridula Gupta, NANOCON 2014 – Third International Conference on Nanotechnology during October 14-15, 2014 organized by Bharati Vidyapeeth University, Pune, India at  Le-Meridien Hotel, Pune
  36. Linearity and analog performance realization of energy efficient TFET based architectures: An Optimization for RFIC Design, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, International Conference on Emerging Electronics (ICEE) held at J N Tata Auditorium, Indian Institute of Science during December 4-6, 2014
  37. Modeling and Simulation of  Nanoscale III-V based Tri Gate Stack MOSFET on Nothing for Improved Analog and Digital Applications, Vandana Kumari, Manoj Saxena, Mridula Gupta, International Conference on Recent Advances in Nanoscience and Nanotechnology (ICRANN-2014), Jawahar Lal Nehru University, New Delhi held during December 15-16, 2014
  38. Dielectric Pocket Tunnel FET: A Reliable Alternative, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, International Conference on Recent Advances in Nanoscience and Nanotechnology (ICRANN-2014), Jawahar Lal Nehru University, New Delhi held during December 15-16, 2014
  39. Analysis of Cylindrical Gate Junctionless Tunnel Field Effect Transistor (CG-JL-TFET), Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta,  12th IEEE India International Conference, INDICON 2015, on Electronics, Energy, Environment, Communication, Computer, Control, (E3-C3) held during December 17-20, 2015 at Jamia Millia Islamia, New Delhi, India (Received Best Paper Award) (Presented)
  40. Merits of designing  Tunnel Field Effect Transistors with Underlap near Drain region, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, 12th IEEE India International Conference, INDICON 2015, on Electronics, Energy, Environment, Communication, Computer, Control, (E3-C3) Held during December 17-20, 2015 at Jamia Millia Islamia, New Delhi, India (Presented)
  41. Investigation of III-V Compound Semiconductor Materials on Analog performance of Nanoscale RingFET, Sachin Kumar, Vandana Kumari, Manoj Saxena, Mridula Gupta, 12th IEEE India International Conference, INDICON 2015, on Electronics, Energy, Environment, Communication, Computer, Control, (E3-C3) held during December 17-20, 2015 at Jamia Millia Islamia, New Delhi, India
  42. Study of Gate Underlap Dielectric Modulated Double Gate Junctionless MOSFET as a Biosensor, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, 18th International Workshop on Physics of Semiconductor Devices (IWPSD 2015) held during December 7-10, 2015 at INDIAN INSTITUTE OF SCIENCE,  Bangalore, India.
  43. Physical Insights into Double Gate (DG) p-i-n TFET Operating States: Modeling and Simulation Study, Upasana, Sakshi Gupta, Rakhi Narang, Manoj Saxena and Mridula Gupta, 18th International Workshop on Physics of Semiconductor Devices (IWPSD 2015) held during December 7-10, 2015 at INDIAN INSTITUTE OF SCIENCE,  Bangalore, India.
  44. Analysis of Gate Underlap Channel Junctionless Double Gate MOSFET as a Sensor, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta, 6th International Conference on Computers and Devices for Communication (CODEC-15) held at Swissotel Kolkata, India during December 16-18,2015.
  45. Modeling and Simulation Study of Short Gate  TFET Architecture Considering the Impact of Mobile Charge Carriers, Understanding Device Physics in Different Operational Regimes, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, 6th International Conference on Computers and Devices for Communication (CODEC-15) held at Swissotel Kolkata, India during December 16-18,2015.
  46. Modeling the Impact of Gate Misalignment in Tunnel Field Effect Transistors" authored by Upasana, Sakshi Gupta, Rakhi Narang, Manoj Saxena and Mridula Gupta, International Conference on Microelectronics Devices, Circuits and Systems (ICMDCS 2017) held at the VIT University, Vellore India from 10th to 12th August 2017
  47. Analytical Modeling and Simulation study of Homo and Hetero III-V Semiconductor based Tunnel Field Effect Transistor, M. Lakshmi Varshika, Rakhi Narang, and Manoj Saxena, accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
  48. Study of Extended Back Gate Double Gate JunctionLess Transistor: Theoretical and Numerical Investigation, Vandana Kumari, Abhineet Sharan Manoj Saxena, Mridula Gupta, accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
  49. Analytical Model for Tapered Gate Electrode Double Gate MOSFET Incorporating Fringing Field Effects, Rakhi Narang, Gokulnath R, Mridula Gupta, and Manoj Saxena, accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
  50. Investigation of sensitivity of Gate Underlap Junctionless DG MOSFET for Biomolecules, Ajay, Rakhi Narang, Manoj Saxena and Mridula Gupta accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
  51. Floating Gate Junction-less Double Gate Radiation Sensitive Field Effect Transistor (RADFET) Dosimeter: A Simulation Study, Avashesh Dubey, Rakhi Narang, Manoj Saxena, and Mridula Gupta, accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
  52. Optically Controlled Silicon On Nothing MOSFET-Numerical Simulation, Vandana Kumari, Manoj Saxena, Mridula Gupta accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.
  53. Simulation Study on Stability aspect of Dual Metal Dual Dielectric based TFET Architectures against Temperature Variations, Upasana, Rakhi Narang, Manoj Saxena, Mridula Gupta accepted in XIX International Workshop on The Physics of Semiconductor Devices (IWPSD 2017) jointly organized by Solid State Physics Laboratory and Indian Institute of Technology Delhi in collaboration with Society for Semiconductor Devices and in association with Jamia Millia Islamia Delhi University, Semiconductor Society (INDIA) and Society for Information Display (SID) to be held during December 11-15,2017 at IIT Delhi.

Paper Published in National conferences: -

  1. Two-Dimensional Analytical Modeling and Simulation of DMG-EPI MOSFET, Kirti Goel, Manoj Saxena, Mridula Gupta and R. S. Gupta, National conference on VLSI Design & Technology, April 12-13, 2004, Bharati Vidyapeeth’s College of Engineering, Paschim Vihar, New Delhi, India.
  2. Two-Dimensional Analytical Modeling and Simulation of a novel structure Triple-Material Gate Stack (TRIMGAS) MOSFET, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, ELECTRO-2005, Emerging Trends in Electronics, BHU, Varanasi, February 3-5, p.134-137, 2005.
  3. Two-Dimensional Analytical Modeling and Simulation of Multiple Material Gate Oxide Stacked MOSFET, R. S. Gupta, Kirti Goel, Manoj Saxena and Mridula Gupta, National Conference on Integrated Broad Band Digital Systems and Networks, NIEC, Delhi, March 18-19, 2005
  4. RF Performance Investigation of Gate Stacked Insulated Shallow Extension (ISE) MOSFET and Bulk: A Comparative Study, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Proceeding of Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 254-258
  5. Design and FPGA realization of Direct Sequence-Spread Spectrum (DS-SS) BPSK Modulator using a Five Stage Gold Code Generator, Rishu Chaujar, Ravneet Kaur, Manoj Saxena and R. S. Gupta, Proceeding of Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2006), pp 213-216.
  6. Scrambled Sequence FPGA based Direct Sequence Spread Spectrum BPSK Modulator: 10 Stage Analysis, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, National Conference on Recent Trends in Electronics and Information Technology, (RTEIT 2006), pp 334-337, 28-29 July 2006, Maharashtra, India.
  7. Exploring the Effect of Negative Junction Depth on Electrical Behaviour of Sub-50-Nanometer Concave DMG MOSFET: A Simulation Study, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), pp. 123-125, 6-8 October 2006, Jaipur, India.
  8. Lateral Channel Engineered Structure- Insulated Shallow Extension (ISE) MOSFET: DC and RF Performance Investigation, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, National Conference on Recent Advancement in Microwave Technique and Applications (Microwave-2006), pp. 119-122, 6-8 October 2006, Jaipur, India.
  9. Effect of transport property on the performance of insulated shallow extension gate stack (ISEGaS) MOSFET, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, pp. 52-57, August 17-18, 2007, Punjab Engineering College, Chandigarh, India
  10. New Concave MOSFET with Transverse Dual Material Gate (T-DMG) in Sub-50nm Regime: A Simulation Study, Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R. S. Gupta, Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, pp. 33-37, August 17-18, 2007, Punjab Engineering College, Chandigarh, India (Best Student Paper Award)
  11. A 2-D Analytical Model for Gate Misalignment Effects on Graded Channel DG FD SOI n-MOSFET, Rupendra Kumar Sharma, Manoj Saxena, Mridula Gupta and R. S. Gupta, Indian microelectronics Society Conference 2007 Theme: Trends in VLSI and Embedded System, August 17-18, 2007, Punjab Engineering College, Chandigarh, India
  12. Development Board-Level Experimentation and Simulation of FPGA based DEBPSK DSSS Modulator: Implementation of 10-Chip Gold Code Sequence Generator, Rishu Chaujar, Ravneet Kaur, Manoj Saxena and R. S. Gupta, Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008) September 26-28, 2008 in New Delhi, India, pp. 255-261.
  13. Simulation of a Novel ISE MOSFET with Gate Stack Configuration, Ravneet Kaur, Rishu Chaujar, Manoj Saxena and R. S. Gupta, Second National Conference on Mathematical Techniques Emerging Paradigm for Electronics and IT Industries (MATEIT 2008) September 26-28, 2008 in New Delhi, India, pp. 291-296.
  14. Solution to CMOS technology for high performance analog applications: GEWE-RC MOSFET , Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R. S. Gupta, 2nd  National Workshop on Advanced Optoelectronic Materials and Devices, AOMD 2008, art. no. 5075707, pp. 201-205.
  15. Effect of temperature variation on various parameters in Insulated Shallow Extension Silicon On Nothing(ISE-SON)MOSFET:A simulation study, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, National Conference and Workshop on Recent Advances in Modern Communication Systems and Nanotechnology (NCMCN – 2011), January, 06-08, 2011
  16. Performance Comparison of Silicon and SiGe based Double Gate Tunneling Field Effect Transistor with gate stack architecture, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, National Conference and Workshop on Recent Advances in Modern Communication Systems and Nanotechnology (NCMCN – 2011), January, 06-08, 2011
  17. Impact of Localised Charges on the performance of the Si Nanowire Surrounding Gate MOSFET, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, National Conference and Workshop on Recent Advances in Modern Communication Systems and Nanotechnology (NCMCN – 2011), January, 06-08, 2011
  18. Investigation of Linearity Performance of a Double Gate Band to Band Tunnel Field Effect Transistor, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, 15th VLSI Design and Test Symposium, July 7-9, 2011, Wipro Technologies, Pune, India
  19. Analog Performance of Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET: Simulation study, Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, 15th VLSI Design and Test Symposium, July 7-9, 2011, Wipro Technologies, Pune, India
  20. A Wide Temperature Range ( 50-500K ) Analysis For Nanoscale Surrounding Cylindrical Gate MOSFET With Localised Charges, Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, 15th VLSI Design and Test Symposium, July 7-9, 2011, Wipro Technologies, Pune, India
  21. Modeling and Simulation of Dielectric Pocket Silicon On Nothing (DiPSON) MOSFET, Neha Bhushan and Manoj Saxena, 99th  Indian Science Congress held at KIIT University, Bhubneswar during Jan 03 – 07, 2012
  22. Impact of Insulating Layers on Single and Double Gate MOSFET for Improved Short Channel Effect and Hot Carrier Reliability , Vandana Kumari, Manoj Saxena, R. S. Gupta and Mridula Gupta, First National Conference on Recent Developments in Electronics (NCRDE 2013), Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013
  23. High Performance Low Power 6T RAM Cell Using Gate-All Around (GAA) MOSFET , Rajni Gautam, Manoj Saxena, R. S. Gupta and Mridula Gupta, First National Conference on Recent Developments in Electronics (NCRDE 2013), Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013
  24. Performance Investigation of Silicon Nanowire Tunnel FET for Analog and Digital Applications, Rakhi Narang, Manoj Saxena, R. S. Gupta and Mridula Gupta, First National Conference on Recent Developments in Electronics (NCRDE 2013), Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013
  25. NI MULTISIM Implementation of Memristor Based Secured Communication System, Khushwant Sehra Poonam Kasturi Mamta Amol Wagh and Manoj Saxena, Proceedings of National Conference on Advancements in Electronics and Computer Applications NCAECA 2016 (UGC and DiETY Sponsored) held during Feb 04-05, 2016 at Shaheed Rajguru College of Applied Sciences, University of Delhi. Pp. 19-24, ISBN 978-93-5254-496-7 published by M/s Paramount Publishing House
  26. Study of Gate and Drain Controllability over Double Gate (DG)Tunnel FETs through Modeling and Simulation, Upasana, Rakhi Narang, Manoj Saxena and Mridula Gupta, Conference Proceedings of Second National Conference on Recent Developments in Electronics (NCRDE-2017), pp. 160-165, ISBN: 978-81- 933475-3- 9
  27. Impact of High-K Gate Dielectric on Double Gate RingFET (HK-DG-RingFET) Architecture, Sachin, Vandana Kumari, , Manoj Saxena and Mridula Gupta, Conference Proceedings of Second National Conference on Recent Developments in Electronics (NCRDE-2017), pp. 177-180, ISBN: 978-81- 933475-3- 9
  28. Two-Dimensional Surface Potential Model for Gate All Around Junctionless Tunnel Field-Effect Transistor, Ajay, rakhi Narang, Manoj Saxena and Mridula Gupta, Conference Proceedings of Second National Conference on Recent Developments in Electronics (NCRDE-2017), pp. 154-159, ISBN: 978-81- 933475-3- 9
     

Abstracts in National Conferences

  1. Generation Of Arbitrary Waves Using Arduino Due, Arun Chahar, Poonam Kasturi and Manoj Saxena , Poster Presentation in THINK NANO 2016 – National Student Symposium organized by Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science, Bangalore held during March 31, 2016 - April 01, 2016 at IISc, Bangalore
  2. Integration of Mem-Element with SCR based Rectifiers, Khushwant Sehra, Gaurav Kumar Shakya, Poonam Kasturi and Manoj Saxena, Poster Presentation in THINK NANO 2016 – National Student Symposium organized by Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science, Bangalore held during March 31, 2016 – April 01, 2016 at IISc, Bangalore
  3. Simulation and Experimental Verification of Memristor Based XOR Gate, Arushi Gupta, Rishav Kumar Pandey, Divya Goel, Poonam Kasturi, Mamta Amol Wagh, Manoj Saxena, Poster Presentation in THINK NANO 2016 – National Student Symposium organized by Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science, Bangalore held during March 31, 2016 – April 01, 2016 at IISc, Bangalore
  4. Smart Traffic System Design Based On PIC Microcontroller, Himanshu Bhardwaj, Samaa Manzoor Wani, Poonam Kasturi  and Manoj Saxena, Poster Presentation in THINK NANO 2016 – National Student Symposium organized by Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science, Bangalore held during March 31, 2016 – April 01, 2016 at IISc, Bangalore
Conference Organization/ Presentations (in the last three years)
Organization of a Conference/ Workshops etc
 
International Events
  • Joint Secretary and Member - Technical Review Committee - 16th Asia-Pacific Microwave Conference (APMC’2004), University of Delhi, December 15 - 18, 2004, New Delhi, India
  • Member - Local organizing committee - India-Japan Workshop (IJW-2006) on ZnO Materials and Devices, December 18-20, 2006 sponsored by DST (New Delhi) - JSPS (Japan) organized by Department of Electronic Science, University of Delhi South Campus
  • Secretary Mini-Colloquia on Compact Modeling of advance MOSFET structures and mixed mode applications on January 5-6, 2008 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program
  • Secretary The 18th WIMNACT(Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology)-New Delhi, India - Mini-Colloquia on Compact Modeling and Fabrication techniques of advance MOSFET/ HEMT structures, June 04-05, 2009 at University of Delhi South Campus, New Delhi, India sponsored by the IEEE Electron Device Society under its Distinguished Lecturer Program
  • Symposium secretary International Symposium on Microwave and Optical Technology (ISMOT)-2009 , December 16-19,2009 in Hotel Ashok, New Delhi, India  
  • Program Committee Member The Seventh International Conference on Distributed Computing and Internet Technology, Bhubaneswar, India, 9 – 12 February 2011
  • Program Committee Member International Conference on Soft Computing for Problem Solving (SoCProS 2011), Roorkee, India, December 16-18, 2011 http://www.mirlabs.net/socpros11/ 
  • Convener Science Academies Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates, February 17-18, 2012, SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, Dhaula Kuan, New Delhi
  • Member-Organizing Committee International MOS-AK/GSA (India) workshop,  March 16-17, 2012 in JIIT University, Noida, Uttar Pradesh, India
  • Member Technical Program Committee Seventh International Conference on “Bio-Inspired Computing: Theories and Application, 2012 (BIC-TA 2012)” to be held at ABV-Indian Institute of Information Technology and Management Gwalior during December 14 - 16, 2012. http://www.iiitm.ac.in/bicta2012/
  • Secretary Mini-Colloquia on "Compact Modelling Techniques for Nanoscale Devices and Circuit Analysis” Organized by IEEE EDS-Delhi Chapter, New Delhi, India during March 14-15, 2012 held at SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, New Delhi, 110021. The Mini-Colloquia was sponsored by the IEEE Electron Devices Society under its Distinguished Lecturer Program
  • Technical Program Committee Member 10th International Conference on Distributed Computing and Internet Technologies, 6th - 9th February, 2014, Bhubaneswar, Odisha, India.
  • Secretary Mini Colloquia on “Compact Modelling Techniques for Nanoscale Devices and Circuit Analysis” on January 13, 2015, University of Delhi South Campus
  • Member-Technical Program Committee International Conference on 14th -15th Jan, 2016 themed on “Cloud System and Big Data Engineering” at Amity University Uttar Pradesh Noida Campus, http://www.gtie2016.com/committees.html#2  ​
  • International Steering Committee Member – 2019 IEEE International Conference on Modeling of System Circuits and Devices (MOS-AK India 2019) organized by joint chapter of CAS/ED Societies IEEE Hyderabad Section, IIT Hyderabad during February 25-27, 2019.
  • Conference Secretary - XVII International Symposium on Microwave and Optical Technology, ISMOT 2020 to be held during December 15-18, 2020 in New Delhi India.

National Events

  1. Member - Organizing Committee National Symposium on recent advances in microwaves and light waves (NSAML’03) University of Delhi South Campus, New Delhi, October 2003.
  2. Treasurer and Member Organizing Committee Short course on Spice Models for Advanced VLSI Circuit Simulation organized by Department of Electronic Science, University of Delhi South Campus, Dec. 11-12, 2005
  3. Secretary and Member-Technical Programme Committee National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2006) from 22nd March – 25th March 2006, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India
  4. Co-convener and Secretary - National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2008) from 26th September – 28th September 2008, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India
  5. Coordinator - Two-Days Workshop On Quantum Mechanics: Theory and Application during November 21-22, 2008, Organized by Forum for Interdisciplinary Application in Sciences (FiDAS) Deen Dayal Upadhyaya College, University of Delhi, New Delhi Sponsored by Delhi Chapter of the National Academy of Sciences, India.
  6. Co-convener and Secretary - Three days Workshop on Futuristic trends of Quality Control in Information Security Management, Sponsored by CSIR, Govt. of India, October 09-11, 2009 organized by Forum for Interdisciplinary Application in Sciences (FiDAS) Deen Dayal Upadhyaya College, University of Delhi, New Delhi
  7. Member-Organizing Committee National Seminar and Workshop on Integrating Multiple Technologies to Support Teaching and Learning, September 24-26, 2009 organized by Department of Electronics, Maharaja Agarasen College, University of Delhi and sponsored by UGC, Govt. of India
  8. Coordinator - First One-Day National Workshop on Einstein & Special Theory of Relativity, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 06, 2009
  9. Coordinator - Second One-Day National Workshop on Einstein & Special Theory of Relativity, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 07, 2009
  10. Coordinator - Two-Day National Workshop on Fiber Optics and Applications, Sponsored By Delhi Chapter-National Academy of Sciences, India, November 28-29, 2009
  11. Co-convener and Secretary - Third National Conference on Mathematical Techniques: Emerging Paradigms for Electronics and IT Industries (MATEIT-2010) held during January 30-31, 2010, Deen Dayal Upadhyaya College, University of Delhi, Shivaji Marg, New Delhi, India, sponsored By University Grants Commission (UGC), Govt. of India
  12. Convener - First National Workshop On Recent Trends in Semiconductor Devices and Technology, Jointly Organized By Aryabhatta Science Forum, Deen Dayal Upadhyaya College, University of Delhi And IEEE EDS Delhi Chapter, New Delhi, Supported By Integrated Microsystem, Gurgaon, India, Society for Microelectronics and VLSI, New Delhi, February 12-13, 2010
  13. Convener - Second National Workshop On Recent Trends in Semiconductor Devices and Technology, Jointly Organized By FiDAS, Deen Dayal Upadhyaya College, University of Delhi And IEEE EDS Delhi Chapter, New Delhi, Supported By DRDO, Govt of India and Integrated Microsystem, Gurgaon, India held during September 17-18, 2010
  14. Convener - Second National Workshop On Quantum Mechanics: Theory and Application Organized By FiDAS, Deen Dayal Upadhyaya College, University of Delhi, Sponsored By CSIR, Govt of India Supported By IEEE EDS Delhi Chapter, New Delhi and The National Academy of Sciences, India, - Delhi Chapter held during Oct. 22-23, 2010 and October 29-30, 2010
  15. Workshop Coordinator - Three Day Joint Science Academies Lecture Workshop On Frontier in Physics, January 21-23, 2011 jointly Organized by FIDAS, Deen Dayal Upadhyaya College and IEEE EDS Delhi Chapter at SP Jain centre, University of Delhi South Campus, New Delhi
  16. Secretary - First National Workshop On Numerical Methods and Differential Equations in Computational Science (NUMDECS-2011), February 01-05, 2011 Organized by FIDAS, DDU College, Sponsored and Supported by University Grants Commission (UGC), Govt. of India
  17. Member-Organizing Committee NATIONAL SEMINOR ON RECENT ADVANCES IN MICROELECTRONIC DEVICES Organized by Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, Sec-22, Rohini, Delhi-110086 sponsored by Defence Research and Development Organization Ministry of Defence, Government of India.
  18. Convener Science Academies Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates, February 17-18, 2012, SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, Dhaula Kuan, New Delhi
  19. Convener Science Academies Lecture Workshop On Joint Academies Lecture Workshop On History, Aspects and Prospects of Electronics in India, October 12-13, 2012,  SP Jain Centre Auditorium, University of Delhi South Campus, Benito Juarez Road, Dhaula Kuan, New Delhi
  20. Convener Lecture Workshop on Trans-disciplinary Areas of Research and Teaching by  Shanti Swaroop Bhatnagar Awardee, February 01-02, 2013 organized by Deen Dayal Upadhyaya College, University of Delhi sponsored by Council of Scientific and Industrial Research (CSIR), New Delhi and supported by IEEE EDS Delhi Chapter
  21. Convener Third National Workshop On Recent Trends in Semiconductor Devices and Technology, January 19-20, 2013 Jointly organized by Deen Dayal Upadhyaya College, University of Delhi and IEEE EDS Delhi Chapter, New Delhi Sponsored By Defence Research and Development Organization (DRDO), Ministry of Defence, Government of India. Venue: SP Jain Centre, University of Delhi South Campus, Benito Juarez Road, Dhaula Kuan, New Delhi
  22. Secretary First National Conference on Recent Developments in Electronics (NCRDE 2013) is being organized by IEEE EDS Delhi Chapter. The conference will be held at Department of Electronic Science, University of Delhi South Campus, New Delhi during Jan 18-20, 2013 
  23. Convener Fourth National Workshop On Recent Trends in Semiconductor Devices and Technology, September 12-13, 2014 organized by Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi Sponsored By Defence Research and Development Organization (DRDO), Ministry of Defence, Government of India. 
  24. Convener On October 17, 2014, One Day Seminar on “Women in Science: A career in Science”, Organized by Silizium-Electronics Society, Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, supported by IEEE EDS Delhi Chapter and Science Education Panel, Indian Acdemy of Sciences, Bangalore
  25. Convener Second Lecture Workshop on Trans-disciplinary Areas of Research and Teaching by Shanti Swaroop Bhatnagar Awardee, January 30-31, 2015 organized by Deen Dayal Upadhyaya College, University of Delhi sponsored by Council of Scientific and Industrial Research (CSIR), New Delhi and supported by IEEE EDS Delhi Chapter
  26. Convener - One Day Symposium to Celebrate International Year of Light held on October 28, 2015.
  27. Convener - Third Workshop on Quantum Mechanics: Theory and Application during March 13-14, 2016 organized by Silizium-Electronics Society, Deen Dayal Upadhyaya College.
  28. Activities organized as Convener-Science Foundation https://dducollegedu.ac.in/ViewpagePAnel.aspx?MenuId=Q8dDQco9jeHkDT6i1aMwZU9NcU8mu5CI
  29. Activities organized as Program Coordinator-DBT Star College Program https://dducollegedu.ac.in/Viewtopics.aspx?MenuId=OGlqRo1PqJzQF5Yfpvx5Gbc____2OFSeIFK

Participation as Paper/Poster Presenter

  • A 2-D Subthreshold Analytical model for Short Channel Effects in Nanowire MOSFETs (Si, Ge), Gaurav Mahajan, Rakhi Narang, Manoj Saxena, V.K. Chaubey, Nirma University International Conference on Engineering (NUiCONE) 2010, December 09-11, 2010, Nirma University, Ahmedabad
Research Projects (Major Grants/Research Collaboration)
  1. Program Coordinator – DBT Star College worth Rs. 1.04 Crores (2018 - )
  2. Co-Principal Investigator in Contract for Acquisition of Research Services (CARS), DRDO sponsored project entitled “Layout Optimization and Thermal analysis swltchlng applicatlons and LNA Design” 2019-2020 worth Rs. 23 Lakhs (Feb 2019 - )
  3. Co-Principal Investigator in CSIR, Govt. of India sponsored major research project entitled Modelling and Simulation Gate Electrode Engineered  and Dielectric Pocket Steep Threshold swing Device for Low Power Digital Circuit Design and Optical Applications(Letter No. 22(0724)/17/EMR-II dt May 16, 2017) worth Rs. 
  4. Co-Principal Investigator in UGC, Govt. of India sponsored research project entitled Physics Based Modeling and Simulation of Channel Material Engineered Ring FET for Sensing Applications worth Rs. 17,23,000/- On Going - (August 01, 2015 - August 2018)
  5. Principal Investigator in a University of Delhi Sponsored Project under Innovation Project Scheme  entitled “Mathematical Modeling and Simulation of Circular and Non-Circular Gate Geometry Junctionless Nanoscale Transistor and co-integration with Memristor Based Electronic Circuits” worth Rs. 4,00,000/- On Going - (October 01, 2015 – November 2016)
  6. Principal Investigator in a University of Delhi Sposnored Project under Innovation Project Scheme entitled Analytical Modeling, Simulation and Verification of Emerging Nanoscale MULTIGATE Device Structures and Study of Government’s Initiatives for Growth of Electronics In India, Project Code – 202 (2013) worth Rs. 5,50,000/- Completed - (November 2013 – February 2015)
  7. Co-Project Investigator in a DST Sponsored Project entitled Analytical Modelling and Simulation of Sub-100 nm Advance Tunnel FET architecture for RF/ Microwave and Biosensing Applications, (SR/S3/EECE/0062/2012) worth Rs. 31,14,000 Completed - (September 2012 – October 2014)
  8. Co-Project Investigator in a DRDO sponsored Project entitled Analytical Modeling, Simulation and Characterization of Silicon Gate All Around Nanowire MOSFET for ULSI (Ultra Large Scale Integration) Circuit Applications worth Rs. 30,68,000 Completed - (April 2012 – March 2015)
  9. Co-Project Investigator in a DRDO sponsored Project entitled Physics Based Modeling and Simulation of Sub-100 nm recessed channel (RC) and insulated shallow extension (ISE) MOSFET with gate electrode work function engineering structures for high performance applications (ERIP/ER/0803693/M/01/1258) worth Rs. 4.70 lakhs Completed - (October 2010 – July 2012)
  10. Co-Principal Investigator in UGC, Govt. of India sponsored research project entitled Modeling and simulation of Nanoscale Dual Material Gate Insulated Shallow Extension Silicon on Nothing MOSFET for Low voltage low power applications (F. No. 36-258/2008(SR)) worth Rs. 9,22,800  Completed - (May 2009 – April 2012)
  11. Co-Project Investigator in a DRDO sponsored Project entitled Physics Based Modeling Simulation and Electrical Characterization of a Novel Device Architecture: Silicon-On-Nothing MOSFET for Sub-100 nm Device Dimensions (No. ERIP/ER/0303417/M/01) worth Rs. 31.68 Lakhs Completed - (April-2004-December 2007) 
 
Awards and Distinctions
  • Received Smt. Shanti Devi Bhargava Memorial Gold medal for being best candidate in the M. Sc Examination in Electronics in 2000
  • Name appeared in the Golden List of IEEE Transactions on Electron Devices Reviewers for year 2005, 2006, 2008, 2009 and 2010.
  • Received outstanding EDS Volunteer recognition from EDS Chapters in the region in 2012.
  • Received Meritorious Teacher by the Govt. of NCT of Delhi for the Year 2014, based on evaluation comprising of Student Evaluation, Result Evaluation, Self Appraisal and Evaluation by the Principal.  
  • Regional Editor South Asia – IEEE EDS News Letter (2015-2017, 2018-)
  • Senior Member - IEEE
  • IEEE EDS Distinguished Lecturer (2016 - )
  • Fellow IETE (2017 - )
  • Member-EDS Board of Governers, USA (2018-2020)
Association With Professional Bodies

Editing

---

Reviewing

  • Reviewer of IEEE Transactions on Electron Devices, Impact factor: 2.704, Electronic ISSN: 1557-9646, Print ISSN: 0018-9383
  • Reviewer of IEEE Transactions on Circuits and Systems I: Regular Papers, Impact factor: 3.934, Electronic ISSN: 1558-0806, Print ISSN: 1549-8328
  • Reviewer of IEEE Transactions on Circuits and Systems II: Express Briefs, Impact factor: 3.25, Electronic ISSN: 1558-3791, Print ISSN: 1549-7747
  • Reviewer of IEEE Electron Device Letters, Impact factor: 3.753, Electronic ISSN: 1558-0563; Print ISSN: 0741-3106
  • Reviewer of IEEE Journal of the Electron Devices Society
  • Reviewer of EEE Access, Impact factor: 4.098, Electronic ISSN: 2169-3536
  • Reviewer of IEEE Transactions on Circuits and Systems I: Regular Papers Impact Factor: 2.823 ISSN: 1549-8328
  • Reviewer of International Journal of Electronics Letters
  • Reviewer of Microelectronics Journal, Impact factor: 1.284, ISSN: 0026-2692
  • Reviewer of IOP Nanotechnology, Impact factor: 3.399, Online ISSN: 1361-6528, Print ISSN: 0957-4484
  • Reviewer of AEU-International Journal of Electronics and Communications, Impact factor: 2.853, ISSN: 1434-8411
  • Reviewer of Journal of Electronic Materials (Springer Journal), Impact Factor: 1.566 (2017), ISSN: 0361-5235 (print version),
  • Reviewer of Materials Science in Semiconductor Processing, Impact factor: 2.722, ISSN: 1369-8001
  • Reviewer of Journal of Physics D: Applied Physics, Institute of Physics (IOP))
  • Reviewer of Semiconductor Science Technology, Impact Factor: 2.654, Online ISSN: 1361-6641, Print ISSN: 0268-1242
  • Reviewer of Measurement Science and Technology (IOP)
  • Reviewer of Solid State Electronics, Elsevier Science, UK
  • Reviewer of Superlattices and Microstructures, Elsevier Science, UK
  • Reviewer of International Journal of Numerical Modelling: Electronic Networks, Devices and Fields (John Wiley & Sons, Ltd.)  Impact factor : 0.795, Online ISSN:1099-1204
  • Reviewer of IET Micro and Nano Letters
  • Reviewer of Journal of Electrical and Electronics Engineering Research (JEEER)
  • Reviewer of Journal of Electrical Engineering & Technology 
  • Reviewer of MAPAN-Journal of Metrology Society of India
  • Reviewer of International Journal of Science and Technology Education Research
  • Reviewer of Computer Communications (Elsevier) , Impact factor: 2.766, ISSN: 0140-3664
  • Reviewer of Journal of Electronic Materials (Springer Journal), ISSN: 0361-5235 (print version), Impact Factor: 1.566 (2017)
  • Reviewer of IET Circuits, Devices & Systems, Impact Factor: 1.277, Online ISSN 1751-8598, Print ISSN 1751-858X
  • Reviewer of International Journal of Electronics and Communications, Impact Factor – 2.115
  • Reviewer of Advances in Condensed Matter Physics, Impact factor: 0.653, ISSN: 1687-8108 (Print), ISSN: 1687-8124 (Online)
  • Reviewer of Microelectronics Reliability ISSN: 0026-2714, Impact Factor – 1.236
  • Reviewer of Turkish Journal of Electrical Engineering & Computer Sciences, Impact factor: N/A, E-ISSN: 1303-6203, ISSN: 1300-0632
  • Reviewer of Microsystem Technologies- Micro- and Nanosystems Information Storage and Processing Systems, ISSN: 0946-7076 (Print) 1432-1858 (Online), Impact Factor-1.581
  • Reviewer of IETE Technical Review
  • Reviewer of Journal of 3D Printing in Medicine
  • Reviewer of International Journal of Electronics
  • Reviewer of International Journal of Electronics
  • Reviewer of Microsystem Technologies

 

  • Reviewer of International Conference - Asia Pacific Microwave Conference (APMC)-2008, 16-19, December 2008 in Hong Kong Convention and Exhibition Center, Hong Kong, China
  • Reviewer of International Conference - International Symposium on Microwave and Optical Technology (ISMOT)-2009,16-19, December 2009 in Hotel Ashok, New Delhi, India
  • Reviewer for Book Proposal for Universities Press (India) Pvt. Ltd. Hyderabad. (2009 - )
  • Reviewer for The 8th International Conference on Computing, Communications and Control Technologies: CCCT 2010, Jointly with The 16th International Conference on Information Systems Analysis and Synthesis: ISAS 2010, In the Context of The International Multi-Conference on Complexity, Informatics and Cybernetics: IMCIC 2010, April 6th - 9th, 2010 Orlando, Florida USA
  • Reviewer of  National Conference on Recent Trends in Exotic materials (NCRTEM 10), Sharda University Greater Noida-201306, U.P., India
  • Reviewer for 7th International Conference on Distributed Computing and Internet Technologies (ICDCIT – 2011), Bhubaneswar during 9 – 12 February 2011.
  • Member-Review Committee - International Conference on Latest Trends in Nanoscience and Nanotechnology (ICNSNT), 28th -29th  March 2011, Karnataka, India
  • Reviewer of The SPRING 9th International Conference on Computing, Communications and Control Technologies: CCCT 2011  Jointly with The 17th International Conference on Information Systems Analysis and Synthesis: ISAS 2011 In the Context of The 2nd International Multi-Conference on Complexity, Informatics and Cybernetics: IMCIC 2011, March 27th - 30th, 2011 ~ Orlando, Florida USA
  • Reviewer for The 4th International Multi-Conference on Engineering and Technological Innovation: IMETI 2011, July 19th - July 22nd, 2011 – Orlando, Florida, USA
  • Reviewer of International Symposium on Models and Modeling Methodologies in Science and Engineering: MMMse 2011  in the context of The 15th World Multi-Conference on Systemics, Cybernetics and Informatics: WMSCI 2011, July 19th - July 22nd, 2011 – Orlando, Florida, USA
  • Program Committee Member - 10th International Conference on Distributed Computing and Internet Technologies, 6th - 9th February, 2014, Bhubaneswar, Odisha, India. http://www.icdcit.ac.in/archive/2014/cfp/CFP-ICDCIT-2014.pdf 
  • Technical Program Committee-21st International Symposium on VLSI Design and Test
  • (VDAT 2017), 29th JUNE - 2nd JULY 2017, IIT Roorkee, INDIAhttps://www.iitr.ac.in/vdat2017/TPC.htm
  • Program Committee Member - 7th International Conference Soft Computing for Problem Solving - SocProS 2017
  • December 23-24, 2017, Indian Institute of Technology Bhubaneswar, Bhubaneswar http://www.socpros17.scrs.in/program-committee.php 
  • Technical Program Committee-twenty-Second International Symposium on VLSI Design and Test (VDAT-2018), Thiagarajar College of Engineering, Madurai, India.  http://vdat2018.tce.edu/technical.php#schedule 
  • Program Committee Member - 8th International Conference Soft Computing for Problem Solving - SocProS 2018, December 17-19, 2018, Vellore Institute of Technology, Tamil Nadu, India http://socpros18.scrs.in/program-committee.php 
  • Program Committee Member – 2018 International Conference on Signal Processing and ommunication, March 21-23, 2018, Jaypee Institute of Information Technology, JIIT Sector - 128, NOIDA—201301http://www.jiit.ac.in/jiit/icsc/ICSC/tpc-members.php 

Committees and Boards

  • Member of Editorial Board of  International Scholarly Research Network (ISRN) Electronics - http://www.isrn.com/32538140/
  • Expert Member  - Directory of researchers working in the country in the area of Nano Science and Technology, Nano Mission, Department of Science and Technology, Govt. of India
  • Member of Selection Committee - Engineering Sciences for selection of students and faculty members at National level for SRF programme.
  • Jury Member in  3rd National Level Exhibition and Project Competition (NLEPC), DST, Govt. of India, October 08-09, 2013, New Delhi
  • Jury Member in  4th National Level Exhibition and Project Competition (NLEPC), DST, Govt. of India, October 06-08, 2014, New Delhi
  • Jury Member in  5th National Level Exhibition and Project Competition (NLEPC), DST, Govt. of India, December 06-07, 2015, New Delhi
  • Jury Member - 7th National level Exhibition and Project Competition (NLEPC) of INSPIRE Awards-MANAK at Indian Institute of Technology (IIT) Delhi held during February 14-15, 2019.
  • Member-Faculty of Interdisciplinary and Applied Sciences, University of Delhi (2016) for a period of 3 years
  • National Committee Member - 22nd International Symposium on VLSI Design and Test ( VDAT - 2018 ) held during June 28th- June 30th 2018, Department of Electronics and Communication Engineering, Thiagarajar College of Engineering, Madurai – 625 015
  • Publicity Chair - 2018 IEEE Electron Device Kolkata Conference (2018 IEEE EDKCON) held in the The Pride Hotel, Kolkata, India during November 24-25, 2018 organized by IEEE EDS Kolkata Chapter
  • Advisory Committee Member  - 6th International Conference on Signal Processing and Integrated Networks (SPIN 2019) held during 7 - 8 March 2019 by Department of Electronics and Communication Engineering, ASET, Amity University, Sec-125, Noida, Delhi-NCR, India
  • Chaired technical session in one-day seminar on "Life and Works of Prof. M. N. Saha and Prof. S. N. Bose" on 15th September, 2018 organized by Department of Physics, Jaypee Institute of Information Technology, (Deemed University), A-10, Sector-62, Noida, UP-201307
  • International Steering Committee Member – 2019 IEEE International Conference on Modeling of System Circuits and Devices (MOS-AK India 2019) organized by joint chapter of CAS/ED Societies IEEE Hyderabad Section, IIT Hyderabad during February 25-27, 2019.

Memberships

  • Vice Chair – IEEE EDS SRC Region 10 (2016-2017)
  • Regional Editor IEEE EDS Newsletter – Region 10 South Asia (2015-2017, 2018-)
  • Senior Member – IEEE, USA (July 2008 - )
  • MIET - Member – Institution of Engineering and Technology (IET), United Kingdom (UK) (2008-)
  • Member - International Association of Engineers, Hong Kong
  • MInstP - Member – Institute of Physics (IOP), (May 2011 - )
  • Member of Editorial Board of  International Scholarly Research Network (ISRN) Electronics
  • Expert Member  - Directory of researchers, Nano Mission, DST, Govt. of India
  • Associate – Indian Academy of Sciences (IAS), India (2009 – 2012)
  • M. N. A. Sc – Member, National Academy of Sciences India (NASI), Allahabad, India (2009 - )
  • Life Member – Semiconductor Society of India, New Delhi, India
  • Life Member - Indian Science Congress Association (ISCA)

Office Bearer

  • Secretary-IEEE Delhi Section (April 2019 - December 2019)
  • Member-IEEE Delhi Section (January 2018 – March 2019 )
  • Chapter Advisor – The National Academy of Sciences, India – Delhi Chapter (2016 -)
  • Secretary – IEEE EDS Delhi Chapter, New Delhi, India (2010 – 2017)
  • Secretary - Institute of Physics (UK)- Delhi Chapter (2013 - 2014)
  • Executive Committee Member – IET(UK) Delhi Network (2013 - 2014 )
  • Joint Secretary – Society for VLSI and Microelectronics, New Delhi, India (2008- Till date)
  • Joint Secretary and Treasurer – IEEE EDS Delhi Chapter, New Delhi, India (2009)
 

 

 
Other Activities
Workshop/ Seminars/ Conferences Attended:
  • Indian Academy of Sciences, Platinum Jubliee Meeting, Bangalore, November 12-14, 2009
  • Bhabha Centenary Symposium, Tata Institute of Fundamental Research,  Mumbai, India, December 03-05, 2009
  • Indian Academy of Sciences 76th Annual Meeting 2010, Goa, 12 to 14 November 2010
 
Assignment, Notes for Students

B. Sc. Hons. Electronics – CBCS Scheme University of Delhi 2015-2018 - Analog Electronics - Course Outline and Suggested Books